Speaker
Mr
David Merodio Codinachs
(ESA)
Description
The use of SRAM-based FPGAs in space equipment is growing. Their radiation-hardness needs to be assessed for the final application (i.e. design) that is implemented in the FPGA device.
The talk proposes an approach for FPGA designers to predict the SEE rates during the design activities. The first step addresses the computation of the static SEE rates of each architectural block of the FPGA device with the environment information of the target mission. This step follows well-known procedures based on SEE characterization by radiation testing and the use of CREME96.
The second step focuses on the FPGA application-specific calculation. In this part we propose the combination of different tools to help the FPGA developer compute the final SEE rate depending on the design, identifying the critical bits in the FPGA Configuration Memory, user Flip-Flops and the Internal RAM.
This helps to iterate and optimise the design taking into account not only parameters as area, speed and power consumption; but also SEE rates.
Primary authors
Mr
David Merodio Codinachs
(ESA)
Mr
Sotirios Athanasiou
(STMicroelectronics, IMEP-LAHC)
