SEFUW: SpacE FPGA Users Workshop, 2nd Edition

Analysis and Mitigation of SEUs on SRAM-based FPGAs using the VERI-Place tool

16 Sept 2014, 11:30

30m

Newton 2 (European Space Research and Technology Centre (ESTEC))

Design for Space Applications: Tools

Speaker

Prof. Luca Sterpone (Politecnico di Torino)

Description

Single Event Upsets on SRAM-based FPGAs is a hot topic for more than a decade. After different investigations have been performed, a first algorithm for the prediction of SEU error probability on circuits on SRAM-based FPGAs is presented and analyzed by software prediction and fault injection analysis. Experimental results and comparison with other methods such as Xilinx Essential Bits report are provided.

Presentation materials

Slides

VERI_Place_Sterpone_final.pdf