Speakers
Mr
Simon Rizzello
(Airbus S&D)Mr
Steve Parkes
(University of Dundee)
Description
The High Processing Power Digital Signal Processor (HPPDSP) project is an ESA funded project led by AirbusDS with STAR-Dundee Ltd and CG Space. It aims to build a high performance DSP processor suitable for spaceflight applications. STAR-Dundee is responsible for the hardware, FPGA and low level software development.
The HPPDSP is designed around the TI TMS320C6727B processor which is available as a space qualified part. The DSP processor connects to external SDRAM via its EMIF (external memory interface) bus. Peripherals that are directly controlled by the DSP processor are attached to the EMIF bus via an FPGA. Other peripherals that are able to access DSP memory and registers in parallel with the DSP processor are attached to the UHPI (Universal Host Processor Interface) bus of the DSP processor via the FPGA.
A board has been designed incorporating the TMS320C6727 processor, SDRAM memory and a Xilinx Virtex 4 FPGA. The FPGA includes EDAC for the SDRAM memory, memory management, SpaceFibre and SpaceWire interfaces, and other general purpose interfaces. A high sample rate ADC/DAC interface is also included.
The presentation will describe the HPPDSP architecture, the FPGA design and the board design. It will also highlight lessons learnt.
