Mr
Gerard Rauwerda
(RECORE Systems B.V.)
19/09/2014, 09:15
The XentiumDARE ASIC is a proof-of-concept design for a radiation-hardened, fault-tolerant multi-DSP system-on-chip with various subsystems to build a powerful digital signal processing system with high data throughput for on-board payload data processing. The main reconfigurable building blocks for creating a multi-core DSP SoC (ie. Xentium DSP, Network-on-Chip and NoC interfaces) have been...
Mr
Luis Berrojo
(Thales Alenia Space España)
19/09/2014, 10:00
The development status of the SSDP will be described during this talk. The Scalable Sensor Data Processor ASIC development activity is being performed in the frame of a CTP ESA funded project, led by Thales Alenia Space España in collaboration with RECORE Systems, IMEC and Arquimea. The aim of the activity is to design, verify, manufacture, and validate a multi-core payload data processor SSDP...
Mr
Roland Trautner
(ESA/ESTEC)
19/09/2014, 10:20
The Scalable Sensor Data Processor ASIC development activity is accompanied by several ongoing and planned activities related to the development of DSP hardware and software in support of future application cases. This includes the NGAPP activity (see following presentation), planned DSP IP and related software developments (TRP proposal), as well as application case and performance...
Mr
Armin Luntzer
(Department of Astrophysics, University of Vienna (UVIE), Mr
Bernhard Kausl
(RUAG Space Austria (RSA)), Mr
Roland Ottensamer
(Department of Astrophysics, University of Vienna (UVIE)
19/09/2014, 10:50
Astronomical science missions in space usually carry a payload of instruments that generate data at high rates. These high data rates often conflict with the available down-link telemetry budget, so that a number of data processing steps will have to be carried out on board by dedicated payload processing units. One of the potential candidate platforms addressing future demands for on-board...
Mr
Constantin Papadas
(ISD), Mr
Laurent Hili
(ESA), Mr
Mohsin Syed
(Airbus D&S)
19/09/2014, 12:20
Currently Airbus DS GmbH and ISD SA are involved in the development of a Demonstrator Chip for the High Performance Data Processor (HPDP), a reprogrammable array processor IP (XPP from the company PACT XPP Technologies), in the STM 65nm radiation hardened technology. The HPDP demonstrator chip is foreseen by ESA as a test-candidate for the first manufacturing run of the radiation hardened STM...
Mr
Fabrice Cros
(Airbus D&S), Mr
Mathieu Patte
(Airbus D&S), Mr
Raoul Grimoldi
(CGS)
19/09/2014, 14:00
During this talk a comprehensive overview of the results achieved in the HiP CBC study will be presented.
The main objective of the HiP CBC study was to demonstrate the feasibility of a COTS based computer system for payload data processing. The following topics will be addressed :
· Fault mitigation architecture and error recovery strategies
· Design of the demonstrator...
Mr
Simon Rizzello
(Airbus S&D), Mr
Steve Parkes
(University of Dundee)
19/09/2014, 16:20
The High Processing Power Digital Signal Processor (HPPDSP) project is an ESA funded project led by AirbusDS with STAR-Dundee Ltd and CG Space. It aims to build a high performance DSP processor suitable for spaceflight applications. STAR-Dundee is responsible for the hardware, FPGA and low level software development.
The HPPDSP is designed around the TI TMS320C6727B processor which is...
Mr
Roland Trautner
(ESA/ESTEC)
19/09/2014, 16:50
A status update on the overall ESA roadmap for onboard payload data processing will be provided. For DSP related activities, new proposals and approved activities will be set in context with past and ongoing work. Estimates for component / technology availability dates will be provided, and recent adaptations of underlying requirements and development plans will be explained.
Mr
Roland Trautner
(ESA/ESTEC)
19/09/2014, 17:20
The public discussion will allow participants from industry to provide feedback to ESA and DSP day presenters. ESA will specifically ask for feedback on the following topics (TBC):
- SSDP: priorities / schemes for software developments
- NGDSP: modified requirements and new IP for ASIC development
- DSP IP vs. DSP ASIC vs. DSP hard IP in FPGA
- Feedback on updated ESA roadmap
