Name: ESA DSP Day 2014
Start: 2014-09-19T08:30:00+02:00
End: 2014-09-19T18:30:00+02:00
Location: ESA/ESTEC

ESA DSP Day 2014

Friday, 19 September 2014 - 08:30

Monday, 15 September 2014
Tuesday, 16 September 2014
Wednesday, 17 September 2014
Thursday, 18 September 2014
Friday, 19 September 2014

08:30 Registration
Registration
08:30 - 09:00
Room: Newton 2
09:00 ESA introduction – DSP Day - Roland Trautner (ESA/ESTEC)
ESA introduction – DSP Day
- Roland Trautner (ESA/ESTEC)
09:00 - 09:15
Room: Newton 2
09:15 DARE+ Application ASIC / Hardened DSP IP and Tools - Gerard Rauwerda (RECORE Systems B.V.)
DARE+ Application ASIC / Hardened DSP IP and Tools
- Gerard Rauwerda (RECORE Systems B.V.)
09:15 - 10:00
Room: Newton 2 The XentiumDARE ASIC is a proof-of-concept design for a radiation-hardened, fault-tolerant multi-DSP system-on-chip with various subsystems to build a powerful digital signal processing system with high data throughput for on-board payload data processing. The main reconfigurable building blocks for creating a multi-core DSP SoC (ie. Xentium DSP, Network-on-Chip and NoC interfaces) have been prototyped in radiation-hardened CMOS using IMEC DARE180 technology. Originating from the Massively Parallel Processor Breadboarding (MPPB) design, we improved the main reconfigurable building blocks with error correction and detection techniques. Payload processing software examples have been prototyped on the rad.-hard XentiumDARE ASIC, using the Xentium software development tools which includes a C-compiler, (multi-core) instruction-set simulator, and floating-point emulation libraries. The Xentium DSP and Network-on-Chip technology are being integrated in future payload processing systems. Based on MPPB and XentiumDARE evaluations we are improving the IP designs according to the users' needs. We will also talk about envisioned feature updates for e.g. the Scalable Sensor Data Processor.
10:00 Scalable Sensor Data Processor Development Status - Luis Berrojo (Thales Alenia Space España)
Scalable Sensor Data Processor Development Status
- Luis Berrojo (Thales Alenia Space España)
10:00 - 10:20
Room: Newton 2 The development status of the SSDP will be described during this talk. The Scalable Sensor Data Processor ASIC development activity is being performed in the frame of a CTP ESA funded project, led by Thales Alenia Space España in collaboration with RECORE Systems, IMEC and Arquimea. The aim of the activity is to design, verify, manufacture, and validate a multi-core payload data processor SSDP ASIC prototype. The SSDP processor is a Mixed signal SoC including 2 RECORE XENTIUM® VLIW Fixed Point DSP processors and a Leon FT processor, and associated peripherals for memory management and external data exchange. External data interfaces will be based in standard buses well established in the space industry such as SpaceWire, CAN, and SPI. The XENTIUM® subsystem will be connected by means of a RECORE proprietary high performance Network-on-Chip grid, while the LEON subsystem will be based in the traditional AMBA bus architecture. Both subsystems will be interconnected by a NoC/AHB bridge. Analog parts will include fast instrumentation- and housekeeping ADC converters, a 16 channel multiplexer, interfaces to temperature sensors, and a PLL. The purpose of this multi-core processor is to manage the wealth of data collected in future space missions, coping with the stringent radiation requirements of missions such as JUICE. IMEC DARE180 technology has been selected for implementation due to its proven radiation performances, mixed signal capabilities, and the availability of required Analog IP blocks SSDP will take advantage of previous projects like Massively Parallel Processing Breadboard (MPPB), DARE+ Application ASIC, and Next Generation Processing Platform (NGAPP) study. SSDP is conceived to ensure the availability of a high tech processor with the highest degree of flexibility, configurability, connectivity, scalable processing power, highly rad-tolerant, low power consumption, low mass, low volume to cover needs for future missions like JUICE, Lunar missions and Mars Landers.
10:20 Parallel SSDP/DSP related ESA activities - Roland Trautner (ESA/ESTEC)
Parallel SSDP/DSP related ESA activities
- Roland Trautner (ESA/ESTEC)
10:20 - 10:30
Room: Newton 2 The Scalable Sensor Data Processor ASIC development activity is accompanied by several ongoing and planned activities related to the development of DSP hardware and software in support of future application cases. This includes the NGAPP activity (see following presentation), planned DSP IP and related software developments (TRP proposal), as well as application case and performance assessments. A brief overview of these activities will be given.
10:30 Coffee break
Coffee break
10:30 - 10:50
Room: Newton 2
10:50 NGAPP final presentation - Armin Luntzer (Department of Astrophysics, University of Vienna (UVIE) Bernhard Kausl (RUAG Space Austria (RSA)) Roland Ottensamer (Department of Astrophysics, University of Vienna (UVIE)
NGAPP final presentation
- Armin Luntzer (Department of Astrophysics, University of Vienna (UVIE)
- Bernhard Kausl (RUAG Space Austria (RSA))
- Roland Ottensamer (Department of Astrophysics, University of Vienna (UVIE)
10:50 - 12:20
Room: Newton 2 Astronomical science missions in space usually carry a payload of instruments that generate data at high rates. These high data rates often conflict with the available down-link telemetry budget, so that a number of data processing steps will have to be carried out on board by dedicated payload processing units. One of the potential candidate platforms addressing future demands for on-board data processing capabilities was subject to the Next Generation Processing Platform (NGAPP) study. This platform is the Massively Parallel Processing Breadboard (MPPB) architectural concept conceived by Recore Systems, the Netherlands, featuring two of their novel Xentium digital signal processing (DSP) cores in a Network-on-Chip (NoC) infrastructure, which is currently also being investigated by ESA in an effort to integrate it into a space-qualifiable ASIC, dubbed “Scalable Sensor Data Processor” or “SSDP”. The objectives of NGAPP were to evaluate the MPPB with respect to processing performance and capabilities, aiming to evaluate applicability for possible space missions, by subjecting it to software benchmarking and architectural analysis. The presentation will illustrate the flow of the NGAPP study, beginning with an overview of the project's organization by highlighting general background aspects, followed by a selection of potential use cases and necessary science data processing capabilities, along with consequences relating to system requirements. The MPPB and its key features will be presented. In addition, a concept of a lean operating system, conceived as an unexpected output of the study, will be introduced. Finally, the overall system performance will be presented and a set of key points for improvements will be suggested as input to the SSDP with respect to its use as a payload processor for future missions.
12:20 HPDP development status - Laurent Hili (ESA) Constantin Papadas (ISD) Mohsin Syed (Airbus D&S)
HPDP development status
- Laurent Hili (ESA)
- Constantin Papadas (ISD)
- Mohsin Syed (Airbus D&S)
12:20 - 12:40
Room: Newton 2 Currently Airbus DS GmbH and ISD SA are involved in the development of a Demonstrator Chip for the High Performance Data Processor (HPDP), a reprogrammable array processor IP (XPP from the company PACT XPP Technologies), in the STM 65nm radiation hardened technology. The HPDP demonstrator chip is foreseen by ESA as a test-candidate for the first manufacturing run of the radiation hardened STM 65nm process. The idea behind this prototyping activity is not only to verify the functionality of the HPDP chip design, but also to get accustomed to the chip development flow of the future European deep sub-micron process. The prototyping is planned within the ESA Greek Industry Incentive Scheme. It is estimated that the HPDP prototype chip will be available in Q1 of 2015. As the STM 65nm process is planned to be made available as a radiation hardened process in the near future, the current exercise enables Airbus DS and ISD to gain experience with using this technology, to get accustomed to the STM development flow, to identify and avoid any hurdles in the future projects. This exercise also assists in identifying any shortcomings of the proposed design methodology for the STM 65nm process.
12:40 Lunch break
Lunch break
12:40 - 14:00
Room: Newton 2
14:00 HiP COTS based computer final presentation - Mathieu Patte (Airbus D&S) Fabrice Cros (Airbus D&S) Raoul Grimoldi (CGS)
HiP COTS based computer final presentation
- Mathieu Patte (Airbus D&S)
- Fabrice Cros (Airbus D&S)
- Raoul Grimoldi (CGS)
14:00 - 16:00
Room: Newton 2 During this talk a comprehensive overview of the results achieved in the HiP CBC study will be presented. The main objective of the HiP CBC study was to demonstrate the feasibility of a COTS based computer system for payload data processing. The following topics will be addressed : · Fault mitigation architecture and error recovery strategies · Design of the demonstrator based on the SCOC3 and TI C6727 components · Results obtained with the demonstrator: processing performance on the NGDSP benchmarks, radiation tolerance, system availability. We will in particular illustrate the tradeoff between system availability and processing performance. · Way forward for future COTS based architecture
16:00 Coffee break
Coffee break
16:00 - 16:20
Room: Newton 2
16:20 HPPDSP Development Status - Steve Parkes (University of Dundee) Simon Rizzello (Airbus S&D)
HPPDSP Development Status
- Steve Parkes (University of Dundee)
- Simon Rizzello (Airbus S&D)
16:20 - 16:50
Room: Newton 2 The High Processing Power Digital Signal Processor (HPPDSP) project is an ESA funded project led by AirbusDS with STAR-Dundee Ltd and CG Space. It aims to build a high performance DSP processor suitable for spaceflight applications. STAR-Dundee is responsible for the hardware, FPGA and low level software development. The HPPDSP is designed around the TI TMS320C6727B processor which is available as a space qualified part. The DSP processor connects to external SDRAM via its EMIF (external memory interface) bus. Peripherals that are directly controlled by the DSP processor are attached to the EMIF bus via an FPGA. Other peripherals that are able to access DSP memory and registers in parallel with the DSP processor are attached to the UHPI (Universal Host Processor Interface) bus of the DSP processor via the FPGA. A board has been designed incorporating the TMS320C6727 processor, SDRAM memory and a Xilinx Virtex 4 FPGA. The FPGA includes EDAC for the SDRAM memory, memory management, SpaceFibre and SpaceWire interfaces, and other general purpose interfaces. A high sample rate ADC/DAC interface is also included. The presentation will describe the HPPDSP architecture, the FPGA design and the board design. It will also highlight lessons learnt.
16:50 ESA summary / DSP roadmap update - Roland Trautner (ESA/ESTEC)
ESA summary / DSP roadmap update
- Roland Trautner (ESA/ESTEC)
16:50 - 17:20
Room: Newton 2 A status update on the overall ESA roadmap for onboard payload data processing will be provided. For DSP related activities, new proposals and approved activities will be set in context with past and ongoing work. Estimates for component / technology availability dates will be provided, and recent adaptations of underlying requirements and development plans will be explained.
17:20 Public discussion / AOB - Roland Trautner (ESA/ESTEC)
Public discussion / AOB
- Roland Trautner (ESA/ESTEC)
17:20 - 18:00
Room: Newton 2 The public discussion will allow participants from industry to provide feedback to ESA and DSP day presenters. ESA will specifically ask for feedback on the following topics (TBC): - SSDP: priorities / schemes for software developments - NGDSP: modified requirements and new IP for ASIC development - DSP IP vs. DSP ASIC vs. DSP hard IP in FPGA - Feedback on updated ESA roadmap