SEFUW: SpacE FPGA Users Workshop, 3rd Edition

FPGA acceleration of computer vision and optimization for European space applications

17 Mar 2016, 12:35

25m

Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

FPGAs: High Performance

Speaker

Dr George Lentaris (National Technical University of Athens, Greece)

Description

Future space robots will rely heavily on computer vision to achieve a high degree of autonomy and efficiency during their mission. Specifically for the Mars rovers of 2020+, ESA plans on using highly accurate localization and mapping algorithms with significantly increased speed. The goal is to provide the rover with the capability to process a mid-resolution stereo image pair in only 1 second, as well as to export a high-definition wide field-of-view depth map in less than 20 seconds. Given the low processing power of the space-grade CPUs, the means to achieve this high-performance goal is to employ high-density space-grade FPGAs and accelerate the computationally demanding kernels of the algorithms by a factor of 10x-1000x. In the project COMPASS of ESA (Code Optimization and Modification for Partitioning of Algorithms developed in SPARTAN/SEXTANT), we perform HW/SW co-design, multi-FPGA partitioning and optimization/customization of various computer vision algorithms for the future Mars rovers. We consider the most prominent of the HW/SW pipelines developed in the past projects SPARTAN and SEXTANT and we re-implement them on space representative hardware focusing on available European devices. To this end, we make use of a LEON3 CPU and, additionally, we take into account the specifications of the new BRAVE NG-FPGA developed for ESA. More specifically, on SW, we use RTEMS on LEON3 and we project the timing results to 150 MIPS. On HW, we use the Synopsys HAPS-54 multi-FPGA board and we impose constraints on the resource utilization of each FPGA to emulate the BRAVE devices. During the optimization phase of COMPASS, we decreased the SW execution time of the algorithm by 90%, whereas for the HW parts, we decreased the FPGA resources by 25%-51% compared to SEXTANT. As a result, today, the complete system (the FPGA parts of both localization & mapping pipelines) will fit in a single space-grade Xilinx FPGA, i.e., the Virtex-5QV. The proposed system can perform 3D terrain mapping in only 17.4sec generating a limited error of 2cm at 4m depth (achieved system speedup 796x), as well as rover localization with less than 2% positional error while running at 1-2 frames per second (achieved system speedup 34-56x). Furthermore, in the multi-FPGA partitioning phase of COMPASS, we demonstrated that it is possible to fit the proposed algorithms in the European space-grade NG-FPGA by employing 1, 2, or 3 BRAVE devices of distinct size each; depending on the specifics of the hypothetical mission (device availability, reconfigurability, and algorithmic performance), we proposed and tested 3 fully-functional multi-FPGA designs, which proved the concept of using European FPGA technology to advance the space applications of the near future.

Presentation materials

Slides

lentaris_sefuw2016.pdf