15–17 Mar 2016
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
All available presentations have been posted

Fast In-Orbit FPGA Reconfiguration via In-Band TM/TC

17 Mar 2016, 14:00
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands

Speaker

Mr Christopher Stender (Fraunhofer Institute for Integrated Circuits IIS)

Description

Flexible payloads often contain one or more reconfigurable FPGAs. In order to use them for various tasks or to quickly deploy new algorithms, a fast FPGA reconfiguration is essential. Unfortunately, satellite telemetry and telecommand (TM/TC) links usually provide only slow data rates for configuration uploads or might not even be available for the payload operator at any time. Thus the upload of a new design, with a size of several megabytes, makes up the largest part of the reconfiguration time. We present a robust in-band “virtual” TM/TC communication system that enables the upload and configuration of new FPGA designs within minutes or even seconds. Cutting dependencies to the satellite’s flight computer or payload controller further simplifies the development and increases the flexibility of the payload. The two lower link layers and parts of the configuration logic are implemented in VHDL. The upper link layers and the management of multiple configurations are realized in software running on a *LEON3FT* soft IP microprocessor. Since the entire digital communication system is implemented in a *Xilinx Virtex-5QV* FPGA, no additional computing hardware is required. To increase the reliability, multiple instances of the virtual TM/TC can be instantiated in the same or other FPGAs. The virtual TM/TC communication system is going to be used for the *Fraunhofer* On-Board Processor (FOBP). Assuming a 1 Mbit/s uplink, a 6 Mbyte *Virtex-5QV* configuration file can be reliable uploaded and configured in less than a minute.

Primary author

Mr Christopher Stender (Fraunhofer Institute for Integrated Circuits IIS)

Presentation materials