15–17 Mar 2016
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
All available presentations have been posted

Dyplo: software driven threaded FPGA development using partial reconfiguration techniques

15 Mar 2016, 16:00
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands

Speakers

Mr Dirk van den Heuvel (Topic Embedded Products)Ms Inge Rutten (Topic Embedded Systems)

Description

Dyplo is a DYnamic Process LOader, enabling software-like programming capabilities on an FPGA such as threading, dynamic process switching and on-the-fly context switching. This allows seamless integration of FPGA logic in a typical software application without the need of deep FPGA design knowledge. A software API gives you full control over functionality run on the FPGA as well as the data transaction of processes running on the FPGA and CPU. The concept behind Dyplo makes use of partial reconfiguration technology, supporting currently only Xilinx FPGA technology. Using an infrastructure that spans both the FPGA and operating system of the processor is a unique solution. This creates all kinds of special capabilities such as functional redundancy, self-repairing systems and time-division-multiplexing of FPGA fabric. This presentation will give you more insight in the concept, a description of the demonstration we will show and a glance of the road ahead where Topic goes with this concept. Topic Embedded Products delivers embedded solutions to accelerate our customers development, forming a complete ecosystem of hardware and software building blocks which are all combinable and compatible. Topic is also one of 10 premier partners world-wide of Xilinx.

Primary authors

Mr Dirk van den Heuvel (Topic Embedded Systems) Ms Inge Rutten (Topic Embedded Systems)

Presentation materials