Speaker
Mr
Adrian Evans
(IROC Technologies)
Description
Flash-based FPGAs such as the ProASCI3L family are frequently used in space applications because the flash storage is highly resistant to single-event effects (SEEs). In this presentation we show the results of a study of an ARM® Cortex-M0+® processor core running a benchmark application (Dhrystone) and tested under a heavy-ion micro-beam. Over a million individual ions were fired both at a plain and a sequential TMR version of the processor. Using special control circuitry, the physical location and exact time of each ion strike was localized and the effect on the test application was studied. We show the reduction in silent data corruption (SDC) and detected-uncorrected errors (DUE) that was achieved in the SEU mitigated (sTMR) processor. It is also shown, using both test-results and fault injection simulations, that single event transients (SETs) are responsible for a significant fraction of the failing cases. The use of the mirco-beam allows designers to identify the specific weak, sensitive areas in their designs with fine granularity.
Summary
We present the radiation test results for an ARM® Cortex-M0+® processor implemented in a ProASCI3L Flash-based FPGA platform, tested using a heavy-ion micro beam.
Primary authors
Mr
Adrian Evans
(IROC Technologies)
Mr
Carlos Urbina Ortega
(SSBV Space & Ground Systems NL)
Mr
Houssem Laroussi
(ESA)
Mr
Kostas Marinis
(ESA)
Co-authors
Dr
Enrico Costenaro
(IROC Technologies)
Mr
Giorgio Magistrati
(ESA/Data Systems Division)
Mr
Kay-Obbe Voss
(GSI)
Dr
Veronique Ferlet-Cavrois
(ESA)
