15–17 Mar 2016
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
All available presentations have been posted

FPGA acceleration in GMV projects for Space Vision-based GNC systems

17 Mar 2016, 12:10
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands

Speaker

Mr David Gonzalez-Arjona (GMV Aerospace and Defence)

Description

Vision Based GNC is becoming the focus of interest for future missions since it will allow mission objectives which cannot be performed by ground because of delays or because the dynamic is too fast for being controlled remotely. On the other hand, the use of information extracted from image in the GNC loop is a challenging issue because images are composed by large amount of data, and, extracting information to be used in the GNC requires complex algorithms that have to be executed at determined frequencies. GMV is applying FPGA acceleration to autonomous GNC system for solving this problem in descent and landing (DL) scenarios under several ESA contracts. The GNC systems are vision-based navigation relying on advanced algorithms and European navigation sensors. The image processing and navigation algorithms developed have been optimized for different scenarios: Itokawa asteroid (Marco Polo-R), Phobos (Phootprint), Dydimos (AIM), the Moon (Lunar Lander and related activities). The GNC systems, where GMV is involved, can use three different vision-based navigation strategies, pure relative navigation, enhanced relative navigation and absolute navigation. They have been implemented in flight representative hardware in a tight and optimal implementation with HW/SW co-design methodology onto a Xilinx XC4V FPGA plus processor device system. As example, within NEOGNC2 project, GR-RASTA-101 avionics has been used for the breadboard prototype, based on Leon2 processor ASIC and XC4VLX100 GR-IO reprogrammed FPGA. The system has been tested in real time testbench available at GMV with simulated images. In addition, HIL tests with a mock-up of Phobos surface and a real camera have validated the performances of the core of the system in a representative environment. In other activities, CPCI-CPU-750 is used as representative HW for hosting complex SW algorithms. Furthermore, within a project of an ECSEL call, GMV participates in the demonstration of in-flight reconfigurable FPGA which uses different vision-based navigation techniques during different mission phases. In this section, the different concepts are presented especially pointing out to the challenges of HW/SW co-design implementation, validation and verification techniques implied in these complex designs.

Summary

Vision Based GNC is becoming the focus of interest for future missions since it will allow mission objectives which cannot be performed by ground because of delays or because the dynamic is too fast for being controlled remotely. On the other hand, the use of information extracted from image in the GNC loop is a challenging issue because images are composed by large amount of data, and, extracting information to be used in the GNC requires complex algorithms that have to be executed at determined frequencies.
GMV is applying FPGA acceleration to autonomous GNC system for solving this problem in descent and landing (DL) scenarios under several ESA contracts. The GNC systems are vision-based navigation relying on advanced algorithms and European navigation sensors. The image processing and navigation algorithms developed have been optimized for different scenarios: Itokawa asteroid (Marco Polo-R), Phobos (Phootprint), Dydimos (AIM), the Moon (Lunar Lander and related activities). The GNC systems, where GMV is involved, can use three different vision-based navigation strategies, pure relative navigation, enhanced relative navigation and absolute navigation.
They have been implemented in flight representative hardware in a tight and optimal implementation with HW/SW co-design methodology onto a Xilinx XC4V FPGA plus processor device system. As example, within NEOGNC2 project, GR-RASTA-101 avionics has been used for the breadboard prototype, based on Leon2 processor ASIC and XC4VLX100 GR-IO reprogrammed FPGA. The system has been tested in real time testbench available at GMV with simulated images. In addition, HIL tests with a mock-up of Phobos surface and a real camera have validated the performances of the core of the system in a representative environment. In other activities, CPCI-CPU-750 is used as representative HW for hosting complex SW algorithms. Furthermore, within a project of an ECSEL call, GMV participates in the demonstration of in-flight reconfigurable FPGA which uses different vision-based navigation techniques during different mission phases.
In this section, the different concepts are presented especially pointing out to the challenges of HW/SW co-design implementation, validation and verification techniques implied in these complex designs.

Primary author

Mr David Gonzalez-Arjona (GMV Aerospace and Defence)

Presentation materials