European Workshop on On-Board Data Processing (OBDP2019)

When a CPU is not enough: hardware data compression for PLATO

26 Feb 2019, 16:30

1h

Erasmus (European Space Research and Technology Centre (ESTEC))

Poster presentation Data Reduction and Compression Poster Session and Exhibit

Speakers

Roland Ottensamer (University of Vienna) Dominik Loidolt

Description

PLATO (Planetary Transits and Oscillations of Stars) is an ESA-M mission which is currently being built. Its scientific goal is the discovery of a large number of exoplanetary systems down to terrestrial planets by means of photometric transits. To do so, the spacecraft has 26 cameras to cover a large part of the sky, each one consisting of 4 CCDs with 4510x4510 pixels each. These are read at equal intervals of 25 seconds to measure changes in the stellar brightness.

Several Data Processing Units (DPUs) are used to extract many thousands of smaller windows (imagettes) with the observed stars, reducing the amount of data from several Gigabytes down to 25 MB for each exposure. After this step, the remaining data are sent to the Instrument Control Unit (ICU), where they are lossless compressed. The amount of data to compress is still too large to be processed within the available CPU resources, hence a specialized hardware data compressor was developed using a RTAX-2000 Field Programmable Gate Array (FPGA).

This hardware compressor, which ensures the fast compression of the data, is realized as a separate electronics board developed in collaboration of IWF Graz and the University of Vienna. Even if the implementation of the compression algorithm is in hardware, we are still limited by the speed of the interfaces and the amount of local memory. We had to consider these restrictions when we devised the algorithm.

Basically, the implemented compression decorrelates the data temporally with a running average that has an exponential tail, resulting in an almost geometric distribution of the residuals. This is a suitable input for the Golomb encoder, which we decided to use as it allows live code generation that is faster in FPGA than if look-up tables were used. The set of parameters that control the filter and the encoder are semi-adaptive, i.e. they adjust to the data in certain intervals.

We show how the compressor is implemented and tested. We also explain the details of the algorithm and the implementation specifics in the FPGA.

Summary

We give an overview of the hardware data compressor for PLATO.