Speaker
Description
We present the deep learning platform (N2D2) and the neural network hardware IPs (PNeuro and DNeuro) developed at CEA, which are specifically tailored to design and integrate deep networks in highly constrained embedded systems (using low power GPU, FPGA or ASIC). The software platform integrate database construction, data pre-processing, network building, benchmarking and optimized code generation for various targets. Hardware targets include CPU, DSP and GPU with plain C, OpenMP, OpenCL and TensorRT(+Cuda/cuDNN) programming models as well as our own hardware IPs. We developed the PNeuro, a programmable DSP-like processor targeting ASIC SoCs and the DNeuro, a dataflow RTL library targeting FPGA. Both PNeuro and DNeuro are currently at the demonstrator level, in ASIC and FPGA respectively (DNeuro is shown in the exhibit).
