Speaker
Dr
Sarah Azimi
(Politecnico di Torino)
Description
When particles hit a sensitive region of the ICs, it can lead to the voltage glitch, i.e. Single Event Transient (SET). Flash-based FPGAs are attracting more and more interests due to the immunity of their configuration memory against Single Event Upset (SEU). Flash-based FPGA technologies such as ProASIC3 as the golden core of several space mission project and RTG4 as the newest technology provided by Micro Chip / Microsemi are the focus of our recent research. We dedicated our study to fully characterizing of SET phenomena, identification of SET propagation scenario and its relative Propagation Induced Pulse Broadening (PIPB) effect on circuits implemented on Flash-based FPGAs.
In this work, we investigated SET propagation considering the Convergence-SET. This phenomenon happens when SET pulses propagated through several paths overlaps and join together at a convergence point and worsen the sensitivity of logics in the output cone. Taking to account a typical RISC processor with 1,401 Versatile and 1,156 FF which works at frequency of 42MHz, based on our developed analysis environment for typical SET pulses lower than 1ns, 19.6% of injected SETs has been broadened while reaching to the FF. On the other hand, 4% of the injected SETs creates C-SET phenomena.
Considering these analyses, we propose a mitigation solution based on charge sharing gates insertion into the circuit netlist which is able to decrease the sensitivity with respect to SET pulse propagation without any timing penalization. As a comparison between the RISC Microprocessor mitigated with typical TMR and Guard-Gate techniques and our proposed charge sharing method, timing and area overhead of 18% and 31% for TMR & GG and 0 and 27% for our proposed method has been reported while using our method shows the reduction of 19.6% regarding Wrong functionality of the circuit.
Primary author
Dr
Sarah Azimi
(Politecnico di Torino)
Co-authors
Dr
BOYANG DU
(Politecnico di Torino)
Prof.
Luca Sterpone
(Politecnico di Torino)
