Name: SEFUW: SpacE FPGA Users Workshop, 4th Edition
Start: 2018-04-09T09:30:00+02:00
End: 2018-04-11T17:00:00+02:00
Location: European Space Research and Technology Centre (ESTEC)

SEFUW: SpacE FPGA Users Workshop, 4th Edition

from Monday 9 April 2018 (09:30) to Wednesday 11 April 2018 (17:00)

Monday 9 April 2018

09:30 Registration and Early Morning Networking Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division
Registration and Early Morning Networking Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division
09:30 - 10:00
Room: Newton 1 and 2
10:00 Welcome - David Dangla (CNES) David Merodio Codinachs (ESA)
Welcome
- David Dangla (CNES)
- David Merodio Codinachs (ESA)
10:00 - 10:30
Room: Newton 1 and 2
10:30
10:30 - 11:30
Room: Newton 1 and 2
Contributions

10:30 FPGA experience and SoC design methodology at Airbus Defence & Space. - Ottmar Ried (Airbus Defence & Space GmbH)

10:50 Jena-Optronik Experience Summary on Microsemi RTG4 designs - Johannes Both (Jena-Optronik)

11:10 SpaceFibre, Spectrometer and Camera: Some applications on the RTG4 FPGA - Steve Parkes (University of Dundee)
11:30
11:30 - 12:10
Room: Newton 1 and 2
Contributions

11:30 UVVM - Universal VHDL Verification Methodology. Setting a standard for VHDL testbenches - Espen Tallaksen (Bitvis)
12:10
12:10 - 13:00
Room: Newton 1 and 2
Contributions

12:10 Multiple-clock Domain FPGA Designs: Challenges and Solutions - Reuven Dobkin (vSync Circuits)

12:35 RTL Analysis and CDC Analysis for Maximum Design Efficiency and Quality - Scott Calkins (Blue Pearl Software. Inc)
13:00 Networking Luncheon
Networking Luncheon
13:00 - 14:00
Room: ESTEC Canteen
14:00
14:00 - 15:10
Room: Newton 1 and 2
Contributions

14:00 Build and Debug Highly Reliably FPGA-based Designs - Philipp Jacobsohn (Synopsys)

14:25 Advanced Verification for FPGAs - Simone Catenacci (Mentor, a Siemens Business)

14:50 Exhaustively Verify SEU Mitigation Techniques Using Formal Verification - Mark Handover (Mentor, A Siemens Business)
15:10
15:10 - 15:30
Room: Newton 1 and 2
Contributions

15:10 Evaluation of MATLAB/Simulink and RTL VHDL HDL environment - Klemen Bravhar (ESA) Stephan van Beek (MathWorks)
15:30
15:30 - 15:50
Room: Newton 1 and 2
Contributions

15:30 FUSIO RT: A New Space Modular Computer Core based on Nanoxplore NG-Medium FPGA - Pierre-Eric Berthet (3D PLUS) Pierre-Xiao WANG (3D PLUS)
15:50
15:50 - 16:30
Room: Newton 1 and 2
Contributions

15:50 Analysis and Mitigation of Single Event Upsets in Configuration Memory of Xilinx Kintex7 SRAM-based FPGA - BOYANG DU (Politecnico di Torino)

16:10 Fault injection for space: FT-Unshades2 updates, experiences and roadmap - Hipólito Guzmán-Miranda (Universidad de Sevilla)
16:30 Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division
Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division
16:30 - 17:00
Room: Newton 1 and 2

17:00

17:00 - 18:45
Room: Newton 1 and 2
Tuesday 10 April 2018

08:50 SEFUW Intro - Opening Remarks
SEFUW Intro - Opening Remarks
08:50 - 09:00
Room: Newton 1 and 2
09:00
09:00 - 10:00
Room: Newton 1 and 2
Contributions

09:00 Xilinx On-Orbit Reconfigurable Kintex UltraScale FPGA Technology for Space - Daniel Elftmann (Xilinx)
10:00
10:00 - 10:20
Room: Newton 1 and 2
Contributions

10:00 First Design-In Experiences of Xilinx's, 20 nm, Kintex UltraScale KU060 for Space Applications and 16 nm UltraScale+ RFSoC for Ground Segment - Rajan Bedi (Spacechips Ltd)
10:20
10:20 - 11:10
Room: Newton 1 and 2
Contributions

10:20 Single Event Characterization of a Xilinx UltraScale+ MP-SoC FPGA - Thomas Lange (IROC Technologies)

10:45 Ultra-High Energy Heavy Ions radiation tests on COTS FPGAs at CERN: results for Microsemi ProASIC3 and Xilinx Zynq all-programmable SoC - Antonios Tavoularis (European Space Agency)
11:10 Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division
Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division
11:10 - 11:40
Room: Newton 1 and 2
11:40
11:40 - 12:40
Room: Newton 1 and 2
Contributions

11:40 Microsemi RTG4 Radiation Tolerant FPGAs: Radiation and Qualification Update - Ken O'Neill (Microsemi)
12:40
12:40 - 13:00
Room: Newton 1 and 2
Contributions

12:40 Modern On-Board-Processing based on FPGAs for Flexible Satellite Communication - Florian Rittner (Friedrich-Alexander-Universität Erlangen-Nürnberg)
13:00 Networking Luncheon
Networking Luncheon
13:00 - 14:00
Room: ESTEC Canteen
14:00
14:00 - 15:20
Room: Newton 1 and 2
Contributions

14:00 FPGA Based Multithreading for On-Board Processing - Andrea Guerrieri (EPFL) Bilel Belhadj (Syderal) Pasquale Lombardi (Syderal)

14:40 Controlling Concurrent Change in Aerospace Electronics - Björn Fiethe (IDA TU Braunschweig)

15:00 Overlay Architectures for Space Applications - Jose Sousa (IPbloq)
15:20
15:20 - 16:20
Room: Newton 1 and 2
Contributions

15:20 Review and comparison of design methodologies and hardware implementations on FPGA technologies. Case study: CCSDS compression algorithms for multispectral and hyperspectral images - Antonio Sánchez (IUMA/ULPGC) Yúbal Barrios (IUMA/ULPGC)

15:40 Image compression on reconfigurable FPGA for the SO/PHI space instrument - David Hernandez Exposito (Instituto de Astrofísica de Andalucía - CSIC)

16:00 Implementation of Visual Based Navigation in a CPU-FPGA architecture for planetary landing - Joao Oliveira (Spin.Works)
16:20 Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division
Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division
16:20 - 16:50
Room: Newton 1 and 2
16:50
16:50 - 17:10
Room: Newton 1 and 2
Contributions

16:50 Implementation of a GNSS Space Receiver on a Zynq - Marc Majoral (CTTC)
17:10
17:10 - 17:30
Room: Newton 1 and 2
Contributions

17:10 A Comparison of 65 nm Space-Grade and COTS FPGAs : RTG4 vs. V5QV vs. NG-MEDIUM vs. NG-LARGE vs. IGLOO2 vs. SmartFusion2 - Rajan Bedi (Spacechips Ltd)
17:30 Round Table and Wrap up
Round Table and Wrap up
17:30 - 18:30
Room: Newton 1 and 2

18:45 SEFUW Dinner
SEFUW Dinner
18:45 - 20:45
Room: ESTEC Restaurant
Wednesday 11 April 2018

08:50 SEFUW Intro - Opening Remarks
SEFUW Intro - Opening Remarks
08:50 - 09:00
Room: Newton 1 and 2
09:00
09:00 - 10:00
Room: Newton 1 and 2
Contributions

09:00 From eFPGA cores to RHBD SoC FPGA - JOEL LE MAUFF (NanoXplore)
10:00
10:00 - 11:10
Room: Newton 1 and 2
Contributions

10:00 QUEENS-FPGA: Quality Evaluation of European New SW for the BRAVE FPGA - David Gonzalez-Arjona (GMV Aerospace and Defence)

10:25 High-Performance Benchmarking of the European NG-MEDIUM FPGA - George Lentaris (National Technical University of Athens, Greece)

10:50 An ECSS-Q-ST-60-02C compliant verification flow for scientific projects - Marcin Darmetko (Centrum Badan Kosmicznych PAN (Space Research Centre))
11:10 Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division
Networking Coffee Break sponsored by COMET by CNES and ESA's Data Systems and Microelectronics Division
11:10 - 11:40
Room: Newton 1 and 2
11:40
11:40 - 13:00
Room: Newton 1 and 2
Contributions

11:40 Permanent Fault Handling in SRAM-based FPGAs - Florian Rittner (Friedrich-Alexander-Universität Erlangen-Nürnberg)

12:00 Fuzzy-logic simulation based approach to modelling of fault propagation in FPGAs. - Andrzej Cichocki (Centrum Badan Kosmicznych PAN)

12:20 Reprogrammable Flash-based FPGA on EUCLID mission - Luca Sterpone (Politecnico di Torino) Raoul Grimoldi (OHB ITALIA)

12:40 Advancement on the Analysis and Mitigation of SETs on Flash-based FPGAs - Sarah Azimi (Politecnico di Torino)
13:00 Networking Luncheon
Networking Luncheon
13:00 - 14:00
Room: ESTEC Canteen
14:00
14:00 - 16:00
Room: Newton 1 and 2
Contributions

14:00 Using Open-source Spacewire and RMAP IPs in the PLATO Router and Data compressor Unit (RDCU) - Jorge Tonfat (Space Research Institute / Austrian Academy of Sciences)

14:20 Virtex5QV - Device & High Speed Interfaces Feedbacks - DANILO LAMONACA (Thales Alenia Space Italy)

14:40 Use of FPGAs in a scientific instrument development process: processing, testbenchs, simulators - Damien Rambaud (IRAP CNRS)

15:00 Evaluation of a New Mass Memory Controller Architecture on Space-Grade FPGAs - Lei Jia (Institute of Computer and Network Engineering (IDA), TU Braunschweig, Braunschweig, Germany)

15:20 Comparison between Microsemi RTG4 and Xilinx SIRF - Felix Vermersch (SERMA)

15:40 Radiation Testing and End User Validation of the BRAVE NG-Medium FPGA - Luis Berrojo (Thales Alenia Space in Spain)
16:00 Concluding remarks and closure
Concluding remarks and closure
16:00 - 16:30
Room: Newton 1 and 2

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