Speaker
Dr
Reuven Dobkin
(vSync Circuits)
Description
Inter clock domain crossings inside multiple clock domain design must be treated carefully in order to eliminate synchronization failures and assure design reliability. For space applications, the reliability assurance is crucial, calling for employment of state-of-the art design integration and verification techniques.
The problem is exacerbated by the fact that the synchronization bugs can be possibly generated by an incorrect automatic design optimization during synthesis and P&R stages, especially for designs having high area utilization, leading to low reliability designs.
During the lecture we will survey common synchronization problems that arise during a design that targets a FPGA device. The survey will cover different design stages, starting from the RTL design using FPGA IP modules and down to synthesis, P&R and gate-level verification stages. In addition, we will suggest and discuss possible solutions to the presented problems at each one of the design stages. We will present a possible design methodology, leading to high reliability designs and to a shorter time to market, minimizing the time spent on synchronization bug fixing during lab testing.
Primary author
Dr
Reuven Dobkin
(vSync Circuits)
