Speaker
Mr
Philipp Jacobsohn
(Synopsys)
Description
Deploying FPGAs in high-assurance applications makes it necessary to protect the device against malfunction. SEU mitigation and error monitoring circuitry is a mandatory prerequisite for any FPGA design used in high radiation environments. Designing SEU-tolerant circuits can be done in manual or automated ways by introducing design techniques such as triple-mode-redundancy and safe implementation of state-machines. Important considerations when choosing an appropriate design flow include not only “design time” as well as “designer expertise” but also “area and power increase” for the circuit as it can affect system cost and reliability of the circuit. This paper discusses mitigation techniques available for different types of FPGAs (Antifuse, Flash-EPROM or SRAM), area/power/performance tradeoffs for each technique. This paper will also talk about how to reduce such overheads with right voter logic location, pipelining of error monitoring/detection etc. In addition, it will cover the ability to add debug capabilities within the scope of triplication and allow developers to easily see each triplication and voter to verify and monitor whether the SEU mitigation techniques are working as expected. It will introduce the audience to the Synplify Premier tool which allows to automatically introduce features such as TMR to FPGAs from all major vendors.
Summary
Design automation for creating highly reliable electronic circuits.
Primary author
Mr
Philipp Jacobsohn
(Synopsys)
