Speaker
Dr
Jose Sousa
(IPbloq)
Description
If a reconfigurable architecture is synthesized on commercial of the shelf (COTS) FPGAs it is called an overlay architecture. Overlays are portable, allows the user to abstract from the FPGA resources used, and is orders of magnitude faster to configure compared to FPGAs.
In this communication we present an overlay architecture consisting of one or more RISC-V CPUs and one or more IPBloq Coarse Grained Reconfigurable Arrays (CGRAs). This architecture is designed so that it can be mapped to different FPGA sizes by using a variable number of tiled CPU/CGRA components.
It targets applications that require both intensive control and data processing. The control part is implemented by the CPUs while the intense data processing algorithms run on the CGRAs. Since this architecture is implemented in an FPGA, it allows different types of parallelism: instruction, data and thread level. The ultimate goal is to achieve maximum performance at minimum energy footprint, while using as small a number of FPGAs as possible.
This kind of architecture is highly suitable for space applications. First of all, applications can be developed using the C programming language, which speeds development and facilitates the intervention of domain experts who need to have no knowledge about hardware description languages and FPGA synthesis, place and route. Second, the adoption of an open source ISA such as the RISC-V ISA facilitates the access to CPU technology , which otherwise is fenced by IP rights, making it difficult for SMEs to make valuable contributions in this area. Third and last, by flexibly accelerating compute intensive tasks on IPbloq CGRAs, it is possible to map very large hardware datapaths on small size FPGAs, by partitioning the datapath into small portions that can be sequentiality mapped to the CGRA with very rapid reconfigurations. Moreover, the fast reconfiguration capability makes the present architecture ideal for fault tolerance, by being able to migrate applications between nodes.
Besides presenting the architecture and programming tool, implementation results for two representative algorithms, FFT and K-means clustering will be presented.
Primary author
Dr
Jose Sousa
(IPbloq)
Co-authors
Mr
Joao Lopes
(University of Lisbon)
Mr
Luis Fiolhais
(IPbloq)
Mr
Maxim Hariton
(University of Lisbon)
