Speaker
Dr
Björn Fiethe
(IDA TU Braunschweig)
Description
Space missions have to handle very high data rates due to increased spatial, radiometric and time resolutions of payload instruments already now. To be able to handle this amount of data, final physical values have to be extracted in real time by an autonomous, intelligent and reliable application already on board the spacecraft, adapting itself to the changing needs in a controlled environment. The DFG Research Group FOR 1800 ”Controlling Concurrent Change (CCC)” develops methods and architectures for embedded system platforms supporting concurrent change of applications and platform under the high requirements to real-time, safety, availability, and security. Within this group we demonstrate and evaluate the usability and capabilities of the CCC approach under the safety, reliability and availability requirements of a typical space application. This includes maximizing the use of resource limited HW/SW platforms in a multi-functional and adaptable manner. The ability of SRAM-based FPGAs to support Dynamic Partial Reconfiguration (DPR) allows a very flexible use of the available HW platform in a Time-Space Partitioning (TSP) manner within the very tight constraints of scientific space missions, even for complex algorithms.
The main emphasis is given to the validation of the CCC approach onto a distributed computing platform under a typical space exploration scenario (e.g. planetary surface exploration), which includes real-time and high criticality demands, i.e. optimization has to be performed during runtime onboard. To achieve this, the demonstrator robotic platform DORIS (Demonstrator Of Reconfigurable Integrated Systems) has been equipped with dedicated data sources (cameras), actuators and System on Chip (SoC) processing platforms including reconfigurable HW and SW capabilities, based on ARM technology. This was also driven by the availability of rad-hard ARM-based processors for the extreme space environment, e.g. soft core in FPGAs or future NanoXplore NG large FPGA. Tightly coupled ARM-FPGA systems, e.g. Xilinx Zynq SoC, benefit from high bandwidth interfaces between hard-wired processor cores and the FPGA fabric.
The Genode OS targets safety-critical applications because it enforces a strong isolation between software components. For that reason, it has been decided to use Genode OS in the CCC project. To use the DPR feature of modern FPGAs also within Genode OS, we have made it available for Genode OS running on a hybrid CPU-FPGA SoC device. A framework has been developed to dispatch tasks from software and execute them hardwareaccelerated in the FPGA fabric of the SoC. This extends the utilization of DPR to mixed-critical systems. Additionally, a newly proposed scheduling algorithm optimizes for the objectives latency/throughput and power/energy.
Furthermore, we will demonstrate the usability and capabilities of the CCC approach for evaluating the error resilience of the complete system and reduction of failure rates, also for SEU mitigation. With an appropriate model, we want to calculate the reliability from a given functional graph.
Primary author
Dr
Björn Fiethe
(IDA TU Braunschweig)
Co-authors
Mr
Alexander Dörflinger
(IDA TU Braunschweig)
Prof.
Harald Michalik
(IDA TU Braunschweig)
Mr
Mark Albers
(IDA TU Braunschweig)
