9–11 Apr 2018
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
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Analysis and Mitigation of Single Event Upsets in Configuration Memory of Xilinx Kintex7 SRAM-based FPGA

9 Apr 2018, 15:50
20m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands

Speaker

Dr BOYANG DU (Politecnico di Torino)

Description

Radiation test has been widely used as one of verification methods able to provide accelerated, realistic environment especially for space applications to evaluate device and system reliability against effects induced by charged particles. As for SRAM-based FPGA, one of the popular reconfigurable devices on the market providing high performance and flexibility, Single Event Upset (SEU) in configuration memory is a major concern due to high sensitivity of SRAM cell against radiation effects. Traditional techniques such as Triple Module Redundancy (TMR) and scrubbing introduce large area and performance overhead, previously developed analysis and mitigation methods demonstrated to effectively increase the overall FPGA circuit reliability without adding critical hardware overhead. In this work, radiation test results of Xilinx Kintex7 device using Ultra High Energy (UHE) heavy ion beam is presented with preliminary analysis. The UHE beam was used to emulate the environment of the space application especially of those targeting on deep space exploration. An ARM-based SoC was used as benchmark circuit with a bubble sort application as test program. Two versions of the design have been prepared, namely 1) Plain, original version of circuit design; 2) XTMR, Plain version with Xilinx TMR tool applied. Experimental data and preliminary analysis of the radiation test show that 1) XTMR version has only 50% sensitivity against SEU in configuration memory comparing to Plain version, w.r.t. error rate cross section 2) our analysis tool VERIPlace is able to have an accurate evaluation of the system reliability, calculated as the probability of an error in output when certain of SEUs accumulated in the configuration memory, with both the Plain and XTMR version. Another version of the design with VERIPlace mitigation technique applied is planned in upcoming test for verifying the mitigation effectiveness.

Primary author

Dr BOYANG DU (Politecnico di Torino)

Co-authors

Prof. Luca Sterpone (Politecnico di Torino) Dr Sarah Azimi (Politecnico di Torino)

Presentation materials