Mr
Scott Calkins
(Blue Pearl Software. Inc)
ASIC and System on Chip (SoC) design and verification practices have traditionally been much more rigorous than that of their FPGA counterparts. Mandated by large non-recurring engineering (NRE) fees associated with the manufacturing setup, design teams set up robust verification methodologies that are rigorously followed to avoid errors that could cause an expensive re-spin. With NRE fees in the range of $100’s of thousands to several million depending on the complexity and process node of the ASIC or SoC, there is no room for error.
Satellites by nature are produced in low volume making them an ideal candidate for FPGAs over ASICs and SoCs, however on a satellite there is also no room for error. Unfortunately, many FPGA design flows fail to incorporate the same level of verification as their ASIC counterparts. While the FPGA vendors do supply quality tools for simulation, synthesis and place and route, they are light on verification and thus can miss or highlight problems very late in the design cycle.
The more complex FPGA become, the more complex and sophisticated the tools supporting their development and verification need to be. For example, in space the SpaceWire interconnect (coordinated by the European Space Agency (ESA)) provides a high speed, low power standard serial interface for a wide range of system requirements.
In this talk I will showcase how a verification methodology that includes Super-lint advanced static and formal analysis along with clock domain crossing analysis can highlight potential issues when interfacing between original content and a SpaceWire core.
Super-lint identifies poor coding styles, improper clocks, simulation and synthesis problems, poor testability and other source code issues. FSM analysis automatically extracts and analyzes finite state machines for dead or terminal states and provides a visual representation. X-propagation analysis detects unknown states, often introduced into designs to implement soft resets or to implement power management schemes and are masked during RTL simulation. I will showcase how leveraging a documented verification methodology can pinpoint issues that may go unnoticed in simulation and even worse, in production.
Summary
Summary – Paper describes the benefits of early RTL and CDC Analysis to maximize design efficiency and quality for both FPGA and ASICs.
Presenter
Scott Calkins, FAE Manager, Blue Pearl Software
Scott Calkins has worked in hardware design for 25 years, working and consulting for more than a dozen companies. He successfully developed and put into production 18 ASIC and FPGAs. Former projects ranged from DSP algorithm development, DO-254 designs, to Sonet networking designs, and H.254 video encoders and decoders. He led a team of technical specialists at Avnet as a DSP and Video signal processing specialist for Xilinx. As an FAE for four companies working to support literally hundreds of companies in the US, Europe and Asia, he has worked on a design from every corner in the industry. Graduated Northeastern University with a BSEE and a minor in Computer Science
