Speakers
Mr
Andrea Guerrieri
(EPFL)Mr
Bilel Belhadj
(Syderal)Mr
Pasquale Lombardi
(Syderal)
Description
FPGA (Field Programmable Gate Array) is an attractive technology for high speed data processing in space missions due to its unbeatable flexibility and best performance to power ratio, in comparison to software. However FPGAs suffer from two major drawbacks. First, higher programming effort is required with respect to software and, second, hardware resources need to be allocated for each implemented function in contrast to software functions which can be executed on the same processing hardware. This presentation describes the results of a demonstrator design activity about a reconfigurable platform based on a ZYNQ FPGA. The achieved objective of this activity is to show that modern FPGAs can be exploited as computing resources like any other processing platform and are suitable for data processing applications without being subjected to the above mentioned drawbacks. Exploiting partial dynamic reconfiguration, we have split the FPGA in different regions, each able to configure a different accelerator concurrently and independently from each other. Then, in the same way as software based multiprogrammed and multithreaded systems can dynamically create, schedule and synchronize threads, we have implemented equivalent abstraction mechanisms to create, schedule and synchronize FPGA based hardware threads. In our system, in analogy to classic processor based computing platforms where multiple software threads run in parallel on different cores, abstraction mechanisms allow a software program to run multiple hardware threads in parallel on different FPGA partitions, while not requiring additional programming effort. As a proof of concept test, we have processed Sentinel-2 Multi Spectral Imager (MSI) Level-1C data available in the Copernicus Open Access Hub to generate Level-2A scene classification map. On the same computational platform, we have achieved 40 times acceleration factor and more than 10 times better energy efficiency when using software controlled FPGA threading in place of full software implementation. The design is fully portable and can be mapped onto other FPGAs integrating partial reconfiguration technology.
This activity has been carried out as a joint collaboration between EPFL LAP and Syderal in the frame of the SWIFT (SoftWare Initiated FPGA Threading) project, funded by the Swiss State of Secretariat for Education Research and Innovation (SERI) within the Positioning Measures initiative implemented by the Swiss Space Center.
Primary authors
Co-authors
Prof.
Paolo Ienne
(EPFL)
Mr
Sahand Kashani Akhavan
(EPFL)
