SEFUW: SpacE FPGA Users Workshop, 4th Edition

Evaluation of a New Mass Memory Controller Architecture on Space-Grade FPGAs

11 Apr 2018, 15:00

20m

Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Industrial Experiences

Speaker

Mr Lei Jia (Institute of Computer and Network Engineering (IDA), TU Braunschweig, Braunschweig, Germany)

Description

A novel Next Generation Mass Memory Architecture (NGMMA) has been introduced for future space application within the scope of an ESA study (Contract No. AO/1-5975/08/NL/LVH) to cope with the growing demands on very high-speed and huge data volumes of future space-borne instruments. In this context, a new memory controller architecture has been developed and evaluated, which interfaces DDR3 SDRAM-based mass memory and new high-speed SpaceFibre [1] interface. While the first implementation was based on a commercial Xilinx Virtex-6 FPGA, evaluation of the memory controller architecture on space-grade FPGAs will be given. I. INTRODUCTION Typically, mass memory controller architectures are dependent heavily on applied memory technologies and space application specific user interface, which leads to a proprietary design. To improve reusability and adaptivity of the mass memory controller architecture, generic building blocks, i.e. Advanced eXtensible Interface 4 (AXI4) interconnect, have been included and a novel partition-based fault-tolerant mass memory controller architecture has been developed, the so-called Partition Controller. The Partition Controller (depicted in Figure 1) consists of Central DMA Controller, Microblaze CPU, DDR3 Memory Interface, SpaceFibre (SpFi) Interface, SpFi Interface Controllers and some other generic IP cores. It uses Direct Memory Access (DMA) transfers, which can be split into multiple single transactions by means of a Scatter-Gather (SG) operation. Externally, it allows a block-based memory-mapped random direct access to the memory partition over an on-chip interconnect. Due to higher SEE sensitivity of DDR3 SDRAMs compared to standard SDRAMs, a double symbol error detection and correction Reed-Solomon (RS) code has been included in the DDR3 Memory Interface for mitigating SEEs. The Partition Controller was demonstrated and evaluated on a so-called Memory Partition Module (shown in Figure 2). A series of space-grade FPGAs can be considered to implement the mass memory controller. This will be discussed in short in the following section. ![Figure 1: Simplified Partition Controller Architecture][F1] II. SPACE-GRADE FPGA OPTIONS DDR3 SDRAMs are operated with a 1.5 V SSTL I/O standard, which needs to be supported by the FPGA and thus limits the FPGA options. Currently, the rad-hard Xilinx Virtex-5QV [2] and Microsemi RTG4 [3] FPGAs support that I/O standard and thus could be used to implement the Partition Controller. The Virtex-5QV FPGA provides many equivalent features and technologies as Virtex-6 FPGA used in the demonstrator. Furthermore, the NanoXplore BRAVE NG large and the Xilinx Kintex UltraScale XQRKU060 FPGAs will be available in the near future and can be also considered as FPGA options. Additionally, a Triple Modular Redundancy (TMR) processor solution [4] can improve the reliability of mass memory controller. ![Figure 2: Memory Partition Module Demonstrator][F2] REFERENCES [1] A. G. Steve Parkes, Albert Ferrer and C. McClements, “Spacefibre specification draft f3,” in SpaceFibre Specification Draft F3, September 2013. [2] [Online]. Available: https://www.xilinx.com/products/silicon-devices/fpga/virtex-5qv.html [3] [Online]. Available: https://www.microsemi.com/products/fpga-soc/radtolerant-fpgas/rtg4 [4] MicroBlaze Triple Modular Redundancy (TMR) Subsystem, PG268, Xilinx, October 2017. [F1]: http://ntserv1.ida.ing.tu-bs.de/simplified_partition_controller_architecture.svg [F2]: http://ntserv1.ida.ing.tu-bs.de/MPMD2.JPG

Presentation materials

Slides

SEFUW2018_NGMMA_Jia.pdf