Speaker
Mr
DANILO LAMONACA
(Thales Alenia Space Italy)
Description
The electronic systems are becoming more and more complex and in need of new high performance programmable logic devices, with an increased number of internal resources and high speed interfaces.
In TAS-I the Xilinx Virtex5QV device is going to be used on a flight unit and this presentation aims to share with the FPGA space community our experience on two specific aspects : (1) A short overview of the Xilinx Virtex5QV device, focusing from the high speed interfaces configurability (Rocket I/O and DDR2 I/F), on to the analysis of the performances and the results obtained by some dedicated board tests.
(2) A brief user guideline approach regarding the prototyping on the equivalent commercial device.
Summary
- Xilinx Virtex5QV Overview
- Rocket I/O (SerDes)
- DDR2 I/F
- Xilinx Virtex5QV Performance & Feedback
Primary author
Mr
DANILO LAMONACA
(Thales Alenia Space Italy)
Co-authors
Mr
Alessandro Colombo
(Thales Alenia Space Italy)
Mr
SIMONE SALDARINI
(Thales Alenia Space Italy)
