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Description
The MAS-FE (Adaptable Scalable Mixed-Signal Sensor/Actuator Front-End for Micro-C and FPGAs) project, funded by ESA, has reached post-silicon status and an ASIC testchip is currently being validated and characterized. The MAS-FE original concept is that of a space-capable, high performance, flexible front-end ASIC in the 10-100Mps segment that can interface effectively between the analogue world on one side, and with an FPGA or micro-controller at the other end.
The MAS-FE testchip integrates state-of-the-art, space capable, new ADC and DAC converter IPs and it is the central piece of the project. Nominal capabilities for both converters are 100Msps, 15 bit.
This work describes the digital MAS-FE Digital IP block and development/evaluation platform which provides multifunctional signal processing capabilities, easy control of the data flow and strong overall user control of the Digital IP configuration and set-up. This Digital IP block and companion development/evaluation platform is designed with a primary goal of interfacing with, and validating the, MAS-FE ASIC ADC and DAC testchip.
Besides for validating the functionality of the testchip this IP block, together with the testchip, makes for an efficient evaluation environment of the MAS-FE project. Together they form a compact evaluation set up which provides the User with great testing and testchip evaluation capabilities.
IP description and evaluation environment set-up
Digital IP is designed to receive, process and transmit data samples into and out of an FPGA, interfacing with the DAC and ADC in the MAS-FE testchip. FPGA chip is integrated in the Xilinx’s SP605 board which is used in this project. SP605 board is connected on one side to the testchip characterization board through FMC connector. This interface transfers 15 bit sample data in Double Data Rate (DDR) LVDS format at maximum clock rate of 100Msps. Data received corresponds to the data from the testchip’s ADC and data transmitted is the input of the testchip’s DAC converter.
On the other side SP605 board communicates with a PC. SW on the PC side is responsible for data acquisition, processing of the received data, as well for the control of the IP and testchip configuration. The User can control, configure and exercise the Digital IP and testchip working together.
Testchip is also connected to instrumentation devices such as signal generators, oscilloscopes, spectrum analyzer.
Joint set up is shown in the figure 1 and represents FPGA+testchip evaluation environment.
IP architecture
Architecture of the IP (figure 2) can be separated in two logic parts: DAC chain and ADC chain.
DAC chain contains versatile signal generator for generating tone signals, saw tooth signals, simple DC level signals or other arbitrary, software-designed periodic signals. There can be up to two tone signals with arbitrary and independent phase and frequency. Software designed periodic signal can be configured to be any waveform signal. Other components in the DAC chain provide DC offset adjustments and data scaling capabilities.
ADC chain architecture is designed for reception of the data from the testchip’s ADC. Its capabilities encompass signal processing abilities and data forwarding techniques. ADC contains DC signal removal module and module for DC signal addition. At the core of its architecture lays moving average filter. These modules provide on chip data processing which can later be more comprehensively processed on the PC side together with the spectral analysis tools like Fast Fourier Transform.
User control
To further expand capabilities of the IP and facilitate functional validation and User evaluation of the testchip, comprehensive software library for the control of the IP is developed in Octave. This library empowers the User with adding and removing digital blocks of the IP from its main data flow path. One of the possible options is also activation of the internal debug loop which allows debug mode of the IP. User is also granted with the ability to change the contents of the registers inside the FPGA. This way different configurations of the processing blocks can be set which makes for an extra flexibility and user control of the IP.
Future applications
Design and functional capabilities of the digital IP block are such that, apart from validation application, it can also be used as prototyping platform of future SoC: The same VHDL developed and tested in the FPGA can be used, under the form of a Netlist for composition of a full ASIC MAS-FE SoC together with the converters’ IP.
Expected status at presentation time in June 2020 is a working prototype of the testchip + FPGA HW platform, with major Digital IP (FW) and User SW capabilities already in place and validated. Preliminary experimental results will be available by then.
