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AMICSA provides an international forum for the presentation and discussion of recent advances in analogue and mixed-signal VLSI design techniques and technologies for space applications.
In order to mitigate Single Event Effects (SEEs), a series of simulation methods have been proposed to conduct SEE evaluation. Typically, such simulation studies include 1) transistor simulation and 2) HDL simulation. Transistor simulation tools (e.g. TCAD and SPICE) usually enable simulations based on currents and voltages. They are normally used for small circuits with few transistors due to the high computation effort required for larger circuits. HDL simulations are used for large scale circuits. However, error rates and propagation paths may change due to the physical layouts, which are not covered in the typical HDL simulation. In order to overcome these shortcomings, we have proposed a new scheme where the SEE models of logic gates are built in SPICE simulations and the evaluation is conducted in HDL simulations, so that it may achieve both accuracy and efficiency.
The proposed scheme includes three steps: 1) build SEE behavior models for the employed logic gates from SPICE simulations, 2) rebuild the HDL netlists of the target circuits using digital SEE models and 3) conduct HDL simulations to analyse SEE behaviors in large scale circuits.
In the first step, the transient currents corresponding with the radiation intensity will be injected to the sensitive node to indicate SEEs. The voltage changes at the output ports will be recorded to build SEE behavior models. The generated SEE models contain the information about pulse width, output delay and possibilities of errors. The models can be reused to reduce the simulation time of this scheme.
The second step is to rebuild the netlist and generate simulation files. In order to inject the SEEs in the HDL simulation, the SEE models are represented by HDL tasks, which are bound to specific logic gates. The employed logic gates in the netlist will be replaced by the redesigned modules with SEE tasks. In the HDL simulation, the respective tasks will be executed to inject SEEs. In this scheme, we designed scripts tools using Python to carry out this step automatically.
The final step is to conduct the simulation, analyse the results and optimise the designs. A set of SEE models can be used to create an unified simulation environment. By using the same set of SEE modules, we can quickly evaluate and compare the SEE mitigation performance of different circuits without taking weeks or months to conduct transistor level simulations.
In our work, we conduct the HDL simulation using the ISCAS89 benchmark circuits to verify the proposed scheme. In those circuits, the S27 circuit is the smallest, which contains 15 circuit units and the S28584 circuit is the largest, which contains 11448 circuit units. The simulation results in the circuits indicate the effects of the SET and SEU on circuits from small scale to large scale. The time cost of HDL simulation for ISCAS89 benchmark circuits is elaborated. We can evaluate the time required for the HDL simulation by averaging time costs for each SEE injection.
By using HDL models, one million SEEs can be injected into S27 circuit in just 55 s, while it will take 55 hours in S38584. The time required for SEE simulation increases nearly linearly with the scale of the circuits.
The time required for HSPICE to conduct same experiment is also tested in this paper. Take S27 as example, the time required to conduct 1 ms simulation is less that 1 s in the proposed scheme, while the SPICE will take more than 67000 s. The obtained results exhibit the efficiency of the proposed scheme.
The main contributions of this work can be summarised as follows:
This work is supported by the UK Engineering and Physical Sciences Research Council through grants EP/R02572X/1, EP/V034111/1, EP/V000462/1 and EP/P017487/1.
The presentation will cover the achievements from introduction of the Digital Programmable Controller ASIC (DPC) into several space products. Full benefit of DPC introduction, like decentralization of equipment management (cfr SAVOIR reference avionic architecture), is now a reality. CANopen standard implemented as backplane data bus and digital regulation of power supply deployed.
Size & cost of the ceramic hermetic version of the component (being a key factor for constellations) has been addressed through alternative packaging: a non-hermetic BGA type package.
More than 400 flight models Ceramic DPC have been produced. More than 1000 PDC packaged into BGA.
The last TRL(9) step is now crossed as tens of DPC are orbiting totalizing more than 32 years of in orbit operation.
Jan Steinkamp1, Frank Henkel1 , Volker Lück2, Dr. Ralf Symanczyk2
1 IMST GmbH, Carl-Friedrich-Gauss-Str.2-4, 47475 Kamp-Lintfort, Germany
2 TESAT-SPACECOM GmbH & Co. KG, Gerberstraße 49, 71522 Backnang, Germany
IMST and TESAT-Spacecom are working together in a DLR funded R&D project on the establishment of a qualified Mixed-Signal ASIC supply chain for space applications. This project is aimed to achieve the capability approval for IMST as a qualified manufacturer given by the ESCC at the end of 2020.
The capability domain covers the design, manufacturing, inspection, test procedure and screening of the ASIC together with a quality control and traceability procedure.
The ASIC design is based on a qualified and Rad-Hard tested mixed-signal IP library called HARD Lib (Hard Against Radiation Design) with multiple library elements usable for a wide range of applications. The IMST IP library is developed on XFABs XH018 technology and contains data converters, biasing cells, reconfigurable opamp, LVDS driver and receiver, SPI interface, OTP cells, clk PLL, oscillators and special I/O cells. The digital design flow supports a full custom design with standard cell libraries and a post-editing script for a triple mode redundancy implementation.
X-FAB serves as the semiconductor foundry in the supply chain and will support small to high volume wafer lots either on a single-mask set or for low quantities with a reduced price on a MLM-set. For the assembly two sizes of a lead frame CQFP package are supported with 256 pins and 132 pins, respectively. The capability approval includes the full screening of the devices as well as qualification and periodic testing according ESCC9000.
With the described capability domain a faster and more reliable ASIC development, with reduced development risk, can be offered compared to a single type ASIC design and qualification flow.
First publications of the ASIC supply chain have been given on the AMICSA 2014 and 2016 showing the design and results of the evaluation phase. In this publication the qualification phase will be presented together with an introduction of the capability domain.
The representative design for the qualification phase has been developed and will be presented. The wafers are fabricated and the assembly process has been started.
As soon as FinFET technology was shown to be a viable alternative to planar technology for nodes lower than 28nm, the radiation community has begun tests to characterize available technology from manufacturers such as Intel, Samsung, Global Foundries, TSMC and radiation testing and service providers [1][2][3][4]. A reduced SEE sensitivity has been observed due to lower carrier collection in the FinFET structure. TID effects are qualitatively similar to planar technology with a small threshold voltage shift and an increase of subthreshold current and STI induced leakage current. As FinFET are majority carriers displacement damage is not anticipated to be important. But Single Defect or Defect Clusters induced by protons or heavy ions in a nuclear collision may be important to consider in 12nm technology. The influence of a single defect depends upon its position in the channel and may modify the electrical characteristics of a single FinFET.
To elaborate on these aspects, this paper will include a global survey of radiation effects on FinFET technology. The synthesis of available results published in selected reviews (Nuclear Science, …), published in conferences (NSREC, RADECS, IRPS, SELSE..) or other public sources will present the sensitivity to total ionizing dose (TID), displacement damage (DD) and single event effects (SEE).
SEE EFFECTS
As an example, the SEE evaluation of the Kintex Ultrascale+ FPGA from XILINX (manufactured with TSMC’s 16nm FinFET process) promises a good behavior regarding SEE.
However, SEL [8] was observed with a relatively high cross section of 2E-3 on power supplies VccAux=1.8V and VccINT=0.85V. The origin of this sensitivity is probably related to the small depth of the STI in FinEFT technologies and should be investigated further.
TID EFFECTS
For Global Foundry 14nm, King et al [9] has studied TID effects on FinFET transistors, SRAM cells and Ring Oscillators for high and low Vth transistors showing only small variation of Ioff below 100krad. IdsOn/Idsoff ratio is reduced from 1E6 at D=0 to 1E2-1E3 at 1 Mrad. Worst case bias conditions are identified. High threshold voltage devices show a smaller response linked to differences in process.
The available results seem to suggest that FinFET technologies are a good match to the requirements of space applications. However, many of the studies focus on the ground-level reliability, relevant for today’s industry’s hot topics such as automotive. The evaluation of the SEE effects in harsh environments dominated by heavy ions or protons is complicated by the particular 3-D structure of the FinFET cells and the fine-grained sensitive device volumes. The paper will present simulation and analysis methods and tool frameworks that can accurately predict SEE performance for complex cells. Particularly, State-of-the-Art (SOTA) EDA frameworks working at TCAD or transistor-level abstraction levels can produce a very exhaustive picture of the device weaknesses and strengths for analog, digital or mixed-mode designs: cross-section of internal cell transistors with a very fine spatial granularity for each possible state of the cell, particle characteristics and impact angle and so on.
Experimental and simulation results can provide invaluable, actionable data that can be used effectively during the hardening phase of the selected technologies or libraries. In addition to non-destructive Single Event Transient/Upset analysis and hardening, a special consideration will be provided to Single Event Latch-ups as previous tests on the UltraScale+ FPGA shown that this type of event can significantly affect the behaviour of devices implemented on FinFET nodes.
In conclusion, FinFET technologies show a great promise for space applications, provided that their behavior is well studied and critical SEE events such as SELs are managed.
The key features of the BCD6s SOI technology and the radiation performances measured on 4 rad-hard power ICs designed in this technology are presented, followed by an overview of the rad-hard design platform developed within these programs, including the hardened library and rad-hard hard IPs. The supply chain options up to the delivery of QML-V products assembled in high dissipation packages are introduced, with then a perspective on a possible ecosystem for the developments of BCD6s SOI rad-hard Power ASIC and ASSP.
For several decades, Microchip provides one of the industry’s most comprehensive space product portfolio of radiation-hardened and radiation-tolerant solutions that includes high-performance MCUs, MPUs, FPGAs, memories, communication interfaces, frequency and timing solutions, mixed-signal ICs, custom power supplies, diodes, transistors, RF components and more. With product development activities and qualified supply chain in Europe, Microchip France is key contributor to the European space ecosystem delivering European and ESCC qualified solutions.
Fully designed, tested and qualified in Europe, ATMX150RHA is a mixed-signal Technology offer that provides high-performance and high-density solutions for Aerospace and Defense applications. ATMX150RHA covers a digital offer and extends it up to 22 million gates with a comprehensive library of standard logic & I/O cells.
With a set of qualified analog IPs, such as voltage regulators, voltage reference and monitoring devices, clock synthesizer and signal conditioning, ATMX150RHA eases the design of mixed-signal ASICs. The ATMX150RHA is the technology supporting our SAMRH71 and SAMRH707 radiation hardened microcontroller family.
The availability of a 5V to 1.8V regulator and the 5V tolerant IO permits easy re-targeting of obsolete or end-of-life ASICs with 5V core supply. The ATMX150RHA offers some High Voltage possibilities as well with some LDMOS transistors characterized in radiation up to 25V, this can be very useful for Power Management application.
In addition, the Physical Design Kit (PDK) enables customers to develop their own analog blocks and use the Microchip Space Multi-Project Wafer (SMPW) services, named PER and PFR that are making easy the access to prototypes
In this presentation we will describe all the features of this technology
Mixed-signal Technology
• Up to 22 usable Mgates (equivalent NAND2)
• Comprehensive library of standard logic & I/O cells
• Memory cells compiled (ROM, SRAM, DPRAM, and Register File Memory)
• 450 MHz PLL (PLL400MRHA)
• Operating voltage 1.8±0.15V for the core and 5±0.5V,3.3±0.3V, 2.5±0.2V for the periphery
• High voltage possibilities (LDMOS transistors up to 25V characterized)
• High-speed LVDS buffers 655 Mbps in compliance with the TIA/EIA-644-A standard
Radiation Performances
• No single event latch-up below LET threshold of 78 MeV/mg/cm² at 125°C;
• TID test up to 300kRads (Si) for 1.8V and 3.3V devices, and 150kRads (Si) for 5V and HV I/O, according to Mil-Std 883 TM1019
Analog and Digital IP blocks
• PLL400MRHA - 40-450 MHz PLL
• ADC12RHA - ADC 12-bit 1 Msps
• DAC12RHA - DAC 12-bit 1 Msps
• MUX8RHA - 8-channel analog multiplexer, bandwidth 10 MHz
• OSCRC10MRHA - Programmable 4/8/10/12 MHZ RC oscillator, ±1% frequency variation over temperature
• OSCRC32KRHA - 32 kHz RC oscillator
• BG1V2RHA - 1.215V Bandgap voltage reference, max temp. coef 90 ppm/°C
• REG200RHA - Linear voltage regulator from 3-5.5V to 1.8V, 200 mA
• POR18RHA - Power On Reset 1.8V
Prototyping solution
• PER : Prototyping Enabler Run for ‘Raw’ prototyping on our ATMX150RHA for fabless design house with basic option only (min 1 run/year)
• PFR : Pragmatic offer with a case by case offering, with higher flexibility (start at any time, wafer hold option for design metal fix, documentation …)
Advanced Packaging in house designed in France
• Advanced multi-layers low-noise CQFP and CCGA packages, up to 352 leads CQFP packages, up to 896 lands/columns CLGA/CCGA packages
• Custom packages development (ceramic / plastic)
Quality assurance grades
• Technology node and complete supply chain qualified for space application continuously monitored and maintained at the highest quality level in Europe
• ATMX150RHA ASICs are available in several quality assurance grades, such as Mil-Prf 38535 QML-Q and QML-V - SMD:5962-20B01 for digital domain - and ESCC 9000 - ESCC DS:9202/083 for digital and extended analog domain (on going)
Weeroc has designed several analogue and mixed signal IP blocks in Microchip ATMX150RHA technology with support of CNES. These IP blocks has been tested for electrical performances, temperature variation and irradiation up to 100krad.
The test vehicle is composed of:
- Two different kind of bandgap
- A 10-bit 10MHz SAR ADC
- A 500MHz-bandwidth switch
One bandgap is a low surface trimmable allowing to adjust the value based on process parameters and user requirement to have an optimized reference. The second bandgap is a large generic bandgap that is not trimmable but optimized for room temperature and minimizing dispersion over a -40°C to +125°C temperature span.
SAR ADC is using a capacitance ladder as a C-2C DAC, a fast low-offset comparator and an asynchronous state machine handling the approximation sequence. ADC requires a differential input and provides a 10-b parallel output. A conversion signal active on rising edge triggers the track and hold and the approximation state machine. A conversion done signal is asynchronously provided when conversion is done and data are available. Data remains available on output until next conversion is started.
High Frequency switch is a 5V analogue I/Os 3.3V digital control switch with a RDSON lower than 20 Ohm and an isolation over 70dB at DC and in the 60dB range at 10MHz. That switch is embedded both in an 8-to-1 analogue multiplexer and in a quad switch component.
These blocks will be detailed and measurement results of electrical performances, temperature and irradiation hardness up to 100krad will be presented for each of these blocks.
In contrast to a pure digital ASIC design flow, which is highly regarded as a top-down design methodology, building an analog mixed-signal complex function usually requires a bottom-up design approach. The latter is based traditionally on a full custom design approach where each functional analog block, after it has been individually designed and verified, it is integrated at a higher level to form the desired electronic function in silicon. Next, the radiation tolerance or hardening of the mixed-signal ASIC is evaluated in silicon as a whole. In 2015, ESA-ESTEC launched the ITT7794, a collaborative industrial R&D program aiming at demonstrating the capability of building radiation hardened (rad-hard) complex mixed-signal analog functions from pre-verified elementary circuit blocks. This approach would otherwise enable a top-down design methodology for mixed-signal rad-hard ASICs that would significantly speed up the design process with a high level of confidence in terms of radiation hardening of the target electronic function. In the frame of the project, a library of rad-hard analog mixed-signal IP blocks has been developed in the ATMX150RHA 150nm CMOS-SOI technology offered by MicrochipTM, by following a rigorous design methodology and a variety of hardening techniques both at design and layout levels. A number of instances from each IP block were laid out on a common silicon substrate in the form of a packaged Technology Characterization Vehicle (TCV) and characterized both electrically as well as against Total Ionizing Dose (TID) and Single Event Effects (SEE) using a heavy-ion cocktail.
We hereby present the results from the electrical verification as well as the radiation testing of each IP block as those obtained from the stand-alone verification of each IP block performed on the TCV. A total number of twelve (12) analog IP blocks were included in the library as implemented on the TCV and presented in Table 1.
Each IP block was electrically characterized over -40°C to 125°C junction temperature range, and over the specified operating voltage range of 3.3V±10% and 1.8V±10% for the analog and the digital parts respectively. The functionality and electrical performance of the IPs was tested in a radiation environment of up to 300 krad (Si) Total Dose at the high dose rate window of 3.6 krad/h and a maximum LET of 62.5 MeV/mg/cm2 using heavy-ions, exhibiting no hard fail or latch up and with minor performance drifts.
The PROMISE project gathers IC experts from 7 European institutions. This project has received funding from the European Union’s Horizon 2020 research and innovation program under grant agreement No 870358. It was launched in early 2020 and is planned to run for the next 3 years. PROMISE stands for PROgrammable MIxed Signal Electronics. It’s tailored to bring a flexible mixed-signal ASIC architecture design ecosystem built on a portfolio of silicon qualified hardened IP blocks to the space community. Moreover, the project is intended to provide a flexible mixed-signal ASIC manufacturing and qualification ecosystem. Last but not the least, PROMISE will deliver IP dissemination, commercialization and intellectual property management to allow efficient reuse of the project’s outcomes by all the space community, and will provide a design environment for new IPs and mid-range ASIC for space applications.
Space Market is living a mutation with the emergence of ‘New Space’, promoting integration/ miniaturization, satellite acceleration, cost-efficient and cost-reduction approaches for all mission types: Earth Observation, Science, Telecom, Navigation and Robotic Exploration. The market for mega constellations is in full swing and several initiatives promoted by different operators are already underway. Accordingly, middle range ASIC solutions are in competition with high performance/high capacity FPGA, new multicore devices and Rad Tolerant parts and COTS. In particular, Mixed Signal ASIC solutions offer functional added value for testability of electronic units and digitalization of full analog functions. The PROMISE project objectives are to optimize the design cost, shorten schedule and de-risk analog and mixed ASIC radhard design, manufacturing and qualification according to the needs of the space industry. PROMISE, led by Thales Alenia Space, encompasses diverse European partners, subcontractors, potential users or solution providers, all top actors of the European Mixed Signal ASIC ecosystem. The partners involved are: TASiS (in Spain who leads the project), top level SMEs as ISD (Greece) and MENTA (France), key technological institutes such as IMEC (Belgium), IT (Portugal) and VTT (Finland); and a leading satellite manufacturer as Thales Alenia Space in France.
PROMISE shall specify a modular architecture based on the DARE180X/XFAB XH018 0.18 micron Mixed Signal HV CMOS Technology that allows the end users to target both simple and complex applications of Mixed-Signal ASICs such as signal conditioning and acquisition, motion control, signal processing, signal synthesis and others. This architecture will pivot around a central eFPGA module that shall provide extra flexibility during the lifetime of the mixed-signal ASIC.
PROMISE shall design an IP library oriented towards the fast design of mixed-signal ASICs by the suitable aggregation of pre-validated modules with the minimum added specific circuitry. It will enable mixed-signal ASIC and ASSP approach. IP reuse will ensure a shortest and secured schedule and de-risk the design hardening for mixed-signal ASIC/ASSP.
As first population for this library, based on the proposed architecture, PROMISE shall design a set of Radiation hardened and reusable analog, high voltage and digital IPs that will cover the most common functions for data acquisition, conditioning, processing and control. This proposed initial portfolio of IPs shall cover, at least, the following functions:
- Digital IPs: Standard digital cells; Standard digital IOs; Non-Volatile Memory (NVM); Embedded Field Programmable Gate Array (eFPGA) core.
- Analog IPs: Analog to Digital Converter (ADC); Digital to Analog Converter (DAC); Phase Locked Loop (PLL); Low Drop Out (LDO) for digital core; BandGap (BG) with second order temperature compensation; Local Oscillator (LO) with no external component and consistent with CAN bus; Power On Reset (POR); High Voltage MOS transistors (HV).
All IPs shall be compliant with the radiation requirement defined within the project. PROMISE shall generate a library of IPs ready to be integrated into fully functional mixed-signal ASIC designs including the Qualified Radhard IPs: digital, analog and high voltage MOS transistors.
Those IPs will be embedded in the Pilot Circuit for electrical performances and radiation tests. The tests will provide:
- Measured Electrical compliance of the IP blocks through the electrical validation of the Pilot Circuit;
- Get the electrical Safe Operating Area for high Voltage MOS;
- Evaluated Radiation hardness of the IP blocks through the radiation evaluation on the Pilot Circuit.
As pursued by the H2020 work-program, this project will generate a new ecosystem fully based on European suppliers and open to all the European Space Industry. PROMISE will enable the development of complete mixed-signal System on Chip solutions for the next generation of space data handling and data processing units. These units, in turn will become the core of new space missions for telecommunications, Earth observation or space exploration. The project results will be presented to all the community on a specific workshop planned for late 2023.
The new PROMISE based circuits will position European space industry on the front line of the development of low cost solutions oriented towards the ‘New Space’ paradigm. As a consequence, the European space actors will be able to take the leading role in the development, production and operation of satellite mega-constellations which are of paramount importance in the XXI century space development. This leading role, assumed without the burden of third party technological dependence, will foster the growth of the European space sector both inside and outside our borders and will generate high quality employment and technological leadership multiplying the return to the European citizens of the investment provided by this H2020 initiative.
This brief presents the experience of integrating two high-performance Data Converter IPs, an ADC and a DAC, in a single rad-hard test-chip. A system-level perspective is taken, underlining the importance of Design-for-Testability (DfT) structures and tuning structures for debugging purposes and achieving first-time right silicon.
Modeling the interactions between domains (PCB, package, analog and digital) is also highlighted as a key to success, particularly for high performance circuits operating at the limits of technology.
The MAS-FE (Adaptable Scalable Mixed-Signal Sensor/Actuator Front-End for Micro-C and FPGAs) project, funded by ESA, has reached post-silicon status and an ASIC testchip is currently being validated and characterized. The MAS-FE original concept is that of a space-capable, high performance, flexible front-end ASIC in the 10-100Mps segment that can interface effectively between the analogue world on one side, and with an FPGA or micro-controller at the other end.
The MAS-FE testchip integrates state-of-the-art, space capable, new ADC and DAC converter IPs and it is the central piece of the project. Nominal capabilities for both converters are 100Msps, 15 bit.
This work describes the digital MAS-FE Digital IP block and development/evaluation platform which provides multifunctional signal processing capabilities, easy control of the data flow and strong overall user control of the Digital IP configuration and set-up. This Digital IP block and companion development/evaluation platform is designed with a primary goal of interfacing with, and validating the, MAS-FE ASIC ADC and DAC testchip.
Besides for validating the functionality of the testchip this IP block, together with the testchip, makes for an efficient evaluation environment of the MAS-FE project. Together they form a compact evaluation set up which provides the User with great testing and testchip evaluation capabilities.
IP description and evaluation environment set-up
Digital IP is designed to receive, process and transmit data samples into and out of an FPGA, interfacing with the DAC and ADC in the MAS-FE testchip. FPGA chip is integrated in the Xilinx’s SP605 board which is used in this project. SP605 board is connected on one side to the testchip characterization board through FMC connector. This interface transfers 15 bit sample data in Double Data Rate (DDR) LVDS format at maximum clock rate of 100Msps. Data received corresponds to the data from the testchip’s ADC and data transmitted is the input of the testchip’s DAC converter.
On the other side SP605 board communicates with a PC. SW on the PC side is responsible for data acquisition, processing of the received data, as well for the control of the IP and testchip configuration. The User can control, configure and exercise the Digital IP and testchip working together.
Testchip is also connected to instrumentation devices such as signal generators, oscilloscopes, spectrum analyzer.
Joint set up is shown in the figure 1 and represents FPGA+testchip evaluation environment.
IP architecture
Architecture of the IP (figure 2) can be separated in two logic parts: DAC chain and ADC chain.
DAC chain contains versatile signal generator for generating tone signals, saw tooth signals, simple DC level signals or other arbitrary, software-designed periodic signals. There can be up to two tone signals with arbitrary and independent phase and frequency. Software designed periodic signal can be configured to be any waveform signal. Other components in the DAC chain provide DC offset adjustments and data scaling capabilities.
ADC chain architecture is designed for reception of the data from the testchip’s ADC. Its capabilities encompass signal processing abilities and data forwarding techniques. ADC contains DC signal removal module and module for DC signal addition. At the core of its architecture lays moving average filter. These modules provide on chip data processing which can later be more comprehensively processed on the PC side together with the spectral analysis tools like Fast Fourier Transform.
User control
To further expand capabilities of the IP and facilitate functional validation and User evaluation of the testchip, comprehensive software library for the control of the IP is developed in Octave. This library empowers the User with adding and removing digital blocks of the IP from its main data flow path. One of the possible options is also activation of the internal debug loop which allows debug mode of the IP. User is also granted with the ability to change the contents of the registers inside the FPGA. This way different configurations of the processing blocks can be set which makes for an extra flexibility and user control of the IP.
Future applications
Design and functional capabilities of the digital IP block are such that, apart from validation application, it can also be used as prototyping platform of future SoC: The same VHDL developed and tested in the FPGA can be used, under the form of a Netlist for composition of a full ASIC MAS-FE SoC together with the converters’ IP.
Expected status at presentation time in June 2020 is a working prototype of the testchip + FPGA HW platform, with major Digital IP (FW) and User SW capabilities already in place and validated. Preliminary experimental results will be available by then.
Key words:
Single chip universal dc-dc controller
High voltage superjunction 200V transistors
Analogue-to-Digital Converters (ADC) are one of the critical components that engineers seek when designing electronic hardware for space flight projects. Today there are very few suitable analogue-to-digital conversion solutions for space-qualified high-speed (from 10Msps onwards) and high-resolution (13 bits and above) applications such as video acquisition, precise motion control and telemetries requiring fast acquisition rate.
Most of the devices used in Europe belong to US companies and, in some cases, are subject to export restrictions. Some initiatives from European suppliers are ongoing, but the preliminary data shared to date show high power consumption levels, above 100mW. Due to the reduced number of flight qualified chip suppliers, there is a trend to use non-space-qualified products known as COTS (commercial-off-the-shelf) that need to be submitted to costly up-screening tests to validate their performance in space environment. Having a radiation hardened ADC with similar characteristics and reduced power consumption (below 100mW) would certainly enable new applications with higher performances. Additionally, it would guarantee European independence on critical space technologies and would reduce the dependence on COTS and associated screening cost and time.
The main goal of this research project is to investigate a solution for high-speed high-resolution analogue-to-digital signal conversion using European technologies, and the subsequent implementation of a radiation-hardened ADC chip for its use in the space environment. Thus, the main project result will be an ADC with a resolution over 13 bits at 10 to 15 MS/s conversion rate, with reduced power consumption (<100mW), implemented with fully European cutting-edge technologies belonging to the Leibniz Research Institute IHP from Frankfurt (Oder), and ready for formal qualification according to the European Space standards. An additional byproduct/objective is the generation of a rad-hard IP core from the ADC, which is a microelectronics functional block that can be integrated in systems-on-chip. The IP form of the ADC will contribute to expand the design platform of IHP’s 130nm technology for space applications, and to reconfirm the promising evaluation results of the basic components in the previous radiation tests.
From the research point of view, this project will provide valuable results on the feasibility assessment of complex mixed-signal designs for space application where the conflicting requirements of high performance, low power consumption and radiation hardness are in place. Additionally, the use of a BiCMOS technology from IHP, where bipolar HBT transistors have at the same time very high performance and an excellent radiation response would contribute to the future European space technology roadmap. Another research result of the project will relate to the optimization of IHP’s design flow for high-performance mixed-signal circuits for space applications such as the proposed ADC.
A digitally assisted continuous-time Delta-Sigma architecture is selected for this purpose. From a space application point of view, the inherent oversampling of this kind of converters can be considered as a multi-vote spread in time that filters SEE at the cost of increasing system noise. The design could take advantage of the fast HBT devices of BiCMOS technology from IHP, combined with new low-voltage and low-power design techniques. The multi-bit quantizer will be replaced by a time-to digital converter based on a high-speed comparator and a delay locked-loop; both components would be reusable in future designs based on the same technology. The loop filter will be implemented with a compact third order continuous-time approach. An ADC with such characteristics is especially demanded for signal conversion in applications involving video data acquisition or high-speed processing of data collected from earth observation satellites, scientific missions, etc.
Key Words:
GaN integrated IC
Half Bridge with driver
power management
The DARE65 Phase-Locked Loop (PLL) is implemented in a 65nm process, operating at 1.2V using a P-sub/Twin-Well commercial CMOS technology. In the PLL, the loop itself is composed of a Voltage-Controlled Oscillator (VCO) based on a ring oscillator, a programmable Charge-Pump (CP) synchronized with a loop divider, a Phase Frequency Detector (PFD) and a 2nd order Low Pass Filter (LPF). Besides the loop, there are three more sub-circuits in the PLL: an input divider, an output divider and a lock detector. The output divider generates a clock signal with a frequency from 6.25MHz – 1200MHz according to the configuration of the three dividers.
The PLL has less than 15ps of period jitter under environmental conditions without Single Event Transient (SET) strikes and 5.1mA of power consumption in the worst case. When radiation-hardened techniques are determined, the power consumption should also be evaluated, otherwise current-starving techniques such as redundancy techniques and increase of driving strength may cause degradation of the general PLL performance.
In the DARE65 PLL design, the radiation-hardening techniques have been considered circuit by circuit. The VCO is implemented based on redundancy techniques, which are firstly averaging-by-redundancy, secondly a large capacitor for voltage-current converter and thirdly triple modular redundancy (TMR) for the ring oscillator. In contrast to the ring oscillator, the voltage-current converter is an analog circuit and it is necessary to apply hardening techniques different from the ring oscillator. In the CP, a series resistor is added at the output in order to attenuate SET-caused fluctuations on the control voltage of the VCO. The radiation hardening is unnecessary for the LPF because it is implemented with MOS capacitance and the active region is connected to the ground node in this PLL design. TMR is applied to the three dividers and lock detector while the PFD is implemented based on radiation-hardened digital cells that have strong driving strength. Compared to the other digital sub-circuits, the PFD state-machine is too complex to use triple modular redundancy, because an additional circuit is necessary for the TMR-based state machine to correct a corrupted state from a SET strike.
For mitigation of Single-Event Latch-up (SEL) and Total Ionizing Dose (TID), diffusion guard-rings are employed to provide SEL hardening and to lower inter-device leakage current for TID conditions up to 100krad.
This radiation-hardened PLL is designed to guarantee less than 280ps of timing error caused by a 60MeV.cm²/mg SET strike. This timing error is verified for a 1200MHz output clock, meaning that the rising edge of the output clock experiences 280ps of shift during the 833.333ps period, which is less than 120° phase deviation. The output divider can be programmed to 1, 2, 4, 8, 16, 32, 64 and 128 of division ratio and the VCO has 800MHz – 1200MHz output frequency range. Due to these circuit performances, users can obtain a wide-range of SET-immune clock signals from the DARE65 PLL. A tape-out of the DARE65 PLL along with other DARE65 IPs is currently under preparation and its performance will be validated by radiation test in the near future.
For several decades, Microchip provides one of the industry’s most comprehensive space product portfolio of radiation-hardened and radiation-tolerant solutions that includes high-performance MCUs, MPUs, FPGAs, memories, communication interfaces, frequency and timing solutions, mixed-signal ICs, custom power supplies, diodes, transistors, RF components and more. With product development activities and qualified supply chain in Europe, Microchip France is key contributor to the European space ecosystem delivering European and ESCC qualified solutions.
Spacecraft and satellites are expanding in complexity to provide commercial and military operators with robust new communication and data capabilities, greater reliability, and faster speeds, while the operators continuously seek to reduce cost, size and weight. In this environment, lowering system development costs while enabling greater capabilities and space system integration are ever more critical.
The introduction of Arm technologies for space applications opens-up new perspectives by enabling the use of the same ecosystem well in place in the consumer and industrial sectors. The SAMRH71 is the first Arm Cortex M7-based rad-hard microprocessor available today on the market. It offers developers the simplicity of a single-core processor and the performance of an advanced architecture without having to implement heavy mitigation techniques as is required for non-space components.
Integration of digital-to-analog converters, analog-to-digital converters, and on-chip non-volatile memory together with a powerful processor core is a key requirement for addressing new challenges in aerospace applications. With the SAMRH707, Microchip provides easy-to-use capabilities in cost-effective, radiation-hardened MCUs. Built to support up to 128kBytes of non-volatile code in its on-chip flash, the SAMRH707 is capable to run as a standalone computer without any need for external memories. Thanks to its embedded 128kBytes flash memory and more than 700kbytes of SRAM, the SAMRH707 enables a high level of integration embedding a >100 DMIPS processor unit with digital signal processing (DSP) capabilities, combined with space connectivity interfaces such as SpaceWire, MIL-STD-1553 and CAN FD, along with analog functions such as a 12-bit Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC), in a small footprint designed for high-level radiation performance, extreme temperatures and high reliability
The SAMRH707 can be seen a new step ahead in the integration of the system directly on a single chip with the integration of the non volatile memory in addition to the standard peripherals. This leads to optimization of the BOM cost by removing external memory requirements from a board, enables reaching much performant memory access speed, minimizing the power consumption of the system…
The Flash memory embedded in the SAMRH707 relies on a conventional eFlash with stacked floating gate. Requiring high voltage for programing and erasing, such flash are quite sensitive to TID, thus limiting the capability to increase the product performances up to 50kRad or higher with the NVM activated.
For many years, Microchip has been developing powerful Flash memories for all the markets. Thanks to this experience in non-volatile-memory development, a SuperFlash technology has been deployed and open a new window for NVM integration on-chip. The key advantage of this NVM technology is that it already demonstrated TID capability up to 100kRad on advanced technology nodes.
Embedding SuperFlash technology in the design of a future system-on-chip for space would open the door to more autonomous, high performance MCUs to serve the space market. Microchip is engaged in this process to deploy new MCU for space application with those advanced technologies.
LIDAR is a distance and speed measurement device using reflection characteristics of emitted light. Space industry is using LIDAR to scan planet surfaces before landing missions, to measure distances between spacecraft and for many other applications. Having the most sensitive detector is critical to measure long distances, particularly in space applications. First LIDAR-dedicated silicon photomultipliers are getting on the market among other detectors such as photomultiplier tubes. However, no dedicated electronics is available so far. Main read-out requirement of LIDAR read-out is an excellent timing resolution and a 2ns double-peak separation. None of the ASICs on the market allows such a fast response. Weeroc has designed a LIDAR dedicated multi-channel read-out chip prototype focusing our R&D on bandwidth and fast return to baseline to fulfil LIDAR requirements.
LIROC ASIC is designed in TSMC 130nm CM013G. This technology has been qualified by CERN for its excellent radiation hardness over total irradiation dose. LIROC is a 64-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM) for LIDAR application.
LIROC allows triggering down to 1/3 of photoelectron (50fC) and provides low-voltage differential trigger output for each channel with an excellent timing resolution (better than 20ps FWHM) and excellent double-peak separation (100% efficiency on 5ns separated single photo-electrons). LIROC allows fast single photon counting over 100MHz per channel.
An adjustment of the SiPM high-voltage (gain) is possible using a channel-by-channel 6-bit DAC connected to the ASIC inputs. Channel-by-channel calibration on the trigger threshold is also possible thanks to 7-bit DACs. LIROC can be calibrated using the dark noise of the SiPM. LIROC features a GHz measurement line composed of an RF preamplifier with pole zero cancellation followed by a fast discriminator and low swing LVDS fast driver. LIROC can be programmed for threshold and several other parameters using a rad-hard I2C interface featuring TMR for SEU detection and correction.
Weeroc measurement shows very good adequation with simulation. Fast photon counting has been validated as well as excellent timing performance and return to baseline to ensure 3ns double peak separation. Liroc can also measure amplitude of incoming signal using a time-over-threshold measurement to have an information on the reflectivity of the target and provide color Lidar images.
Liroc can be hooked up to two CERN PicoTDC to build a full LIDAR receiver system capable of large photon counting at few ps timing resolution and single photon sensitivity with an output data rate up to 20Gbps.
Liroc features will be presented. Architecture of the different blocks will be described and measurement performed will be shown as well as foreseen applications.
To date most of the front-end implementations for spaceborne fluxgate magnetometers are built using a mix of discrete components and multiple integrated circuits. The MFA-3 (Magnetometer front-end ASIC) initiated a first step towards miniaturization, integrating parts of the whole front-end electronics on a single chip. This ASIC is based on an outdated process technology and offers a small measurement range. A further drawback is the limited radiation hardness against single event effects. Since the requirements on sensor front-ends that are used in satellites are rising, performance and miniaturization are key elements. Further radiation hardness and power efficiency are also essential development goals. Therefore, it is crucial to improve the required functionality and integrate it on a single chip. This work describes the design of the next generation front-end ASIC for spaceborne fluxgate magnetometers. This upcoming ASIC is built using a technology with a smaller process node. Further the dynamic range should be increased up to 65000nT.
Fluxgate magnetometers are used to measure the magnetic field. They are made of a soft magnetic ring core and different types of excitation, feedback and sense windings. The excitation coil periodically saturates the soft magnetic ring core at a fundamental frequency of several kHz. The output signal of the sense coil contains odd and even harmonics of the fundamental drive frequency. The even harmonics are proportional to the external magnetic field along the magnetic axis of the sensor. The odd harmonics result from the feed-through signal coupled from the excitation coil and the soft magnetic core to the sense coil. The forward path of the front-end ASIC has to perform the extraction of the magnetic field information by translating the even harmonics into a slowly changing output voltage according to the bandwidth of the magnetometer. Then digital signal processing is used to calculate a feedback signal that is used to compensate the ambient magnetic field. This compensation is done by the feedback path, that creates a loop formed by an additional feedback coil hereby extending the linearity and measurement range of the magnetometer. The feedback path consists of a high resolution DAC (digital-to-analog converter) that controls the feedback coil driver. This coil driver must provide highly linear currents of up to 20mA to compensate the ambient magnetic field. The feedback path is required to have a dynamic range of up to 20bits depending on the mission scenario. To achieve a higher dynamic range than the space qualified predecessor MFA-3 (Magnetometer front-end ASIC) new concepts for the feedback path have been evaluated. The forward path consists of a low-noise amplifier and a medium-resolution analog-to-digital converter. The forward path is currently in the concept phase.
To evaluate different concepts two test chips have been designed and fabricated. The first test chip contains a configurable high-resolution DAC. This DAC is composed of a two-stage Delta-Sigma-modulator that uses a current steering DAC in the final D/A stage. The second test chip contains another high-resolution DAC based on a single-bit D/A-cell realized using a chopped current-steering cell and a circuitry to drive the feedback coil. Further a dedicated block to monitor the system conditions was implemented on chip. To increase the radiation hardness different techniques have been used. The first test chip was hardened by design, taking the degradation mechanisms of different transistor types into account. The second test chip was hardened by the use of guard rings to reduce latch-up events. The overall goal is to achieve a TID (Total Ionizing Dose) immunity of more than 300krad and improve SEL (Single Event Latch-up) up to 50MeV-cm²/mg. Both test chips have been evaluated successfully. The concepts for the feedback path have been adapted due to the outcome of the evaluation phase and will be implemented on the final ASIC. The final front-end ASIC should be able to readout and drive a 3-axis fluxgate sensor. It then contains the forward path and the feedback path for each axis (x-y-z) as well as a system monitoring block. Measurements results based on the proposed concepts as well as a brief outlook of the upcoming MFA development is intended to be shown at the AMICSA.
We present APOCAT, an integrated circuit (IC) for reading out spaceborne photon detectors, i.e., photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs). The circuit can be used in x-ray and gamma-ray detectors, for example, the advanced space-based solar observatory ASO-S. ASO-S shall be launched in 2022 to study solar flares and coronal mass ejections on the Sun. APOCAT is related to SIPHRA, another SiPM/PMT readout circuit. APOCAT has the following main key features: 1. High-rate analog pulse height processing and energy resolved counting, simultaneously and asynchronously, in each channel (1Mcps/channel); 2. Low equivalent noise charge (ENC) for triggering and counting of single photons (<50fC ENC), 3. On-chip ADC (12-bit/2Msps), 4. High radiation tolerance. Samples have been manufactured and the design has been characterized. Work remains for flight model qualification.
This paper describes a new kind of volage clamp IC combining precise regulation with high current capability and it's various application use cases. Special attention is given to thermal design limitations.
The evolution of power distribution in spacecraft goes into direction of modular architecture. Especially the secondary power distribution from the satellite bus to the local consumers can be made more efficient, reliable and failure-tolerant by applying modular design. Such architecture comprises distributed power conversion, which on the other hand makes necessary a distributed voltage protection to safely keep every local supply voltage below the maximum rating of the load. Power lines in modern spaceborne devices are exposed to many potentially harmful events, including consequences of short circuits and single event effects in DC/DC converters. Once a failure occurred, it can further propagate through the architecture. Small voltage protection circuit at the proper place can limit or even prevent such failure propagation.
The voltage protection circuits can be realised using the described small and easy applicable voltage clamp IC. It is a fast and precise adjustable shunt voltage regulator with high current capability and integrated voltage reference. Additionally, the proposed circuit can be used in a variety of other popular applications (see attachment).
The device consists of internal housekeeping block, error amplifier, high-voltage power switch and monitoring block. The device operates in two primary modes: standby and regulation. Only internal housekeeping and the main regulation loop are powered up in standby mode to achieve a supply current consumption of 120 μA (typical). Power-hungry monitoring circuitry is activated only after the detection of an overvoltage event on the protected rail. The device generates “Active” signal if activated, as well as “Alert” signal in case of overvoltage, overtemperature or power transistor overcurrent.
The separation of VCC supply pin and VCL power switch output allows clamping voltage setting as low as 800 mV, while VCC has to be in the range of 3...40 V. The power switch is capable of handling 10 A pulse current with appropriate heating limitations. An external resistor can help dissipating more power and dealing with higher current-voltage product.
Radiation hardening of the device was an integral part of the design process. The fully isolated SOI technology and factory-provided data on total dose behaviour of 1.8 V devices, enclosed layout 3.3 V and LDMOS transistors as well as latchup-immune 1.8 V standard cell library are the foundation, on top of which digital, analogue and power IPs protected against total dose, latchup and single event effects were designed. The protection means for digital signals include triple-mode redundancy and filtering against single event effects and full dielectric isolation of nMOS and pMOS transistors against latchup and inter-transistor leakages. Each analogue node was also protected accordingly to circuit specifics by common topology measures including cascoding to reduce drain-source voltages, reference voltage filtering, static current definition to override SETs, and so on. Various methods of SET-induced current isolation or sharing were used on the layout level. The final design was extensively tested by current injection to ensure single event transient robustness, which is especially important in a device comprising a low-ohmic power switch. The design targets a TID tolerance of 100 krad(Si) and SEE insensitivity for LET up to 60 MeV*cm2/mg.
The design of active adjustable voltage clamp is presented. The proposed device is able to protect power lines from overvoltage event and can also work as a shunt regulator. The device utilises fully isolated SOI technology and methods of radiation hardening by design.
ABSTRACT
This presentation describes the mixed-signal microcontrollers GR716A and GR716B. These microcontrollers target embedded control applications with hard real-time requirements. The GR716A is currently available at prototype level. Extended electrical and radiation characterization is on-going as part of the activity Microcontroller for embedded space applications, initiated and funded by the European Space Agency (ESA). The GR716B is a further development of the GR716A microcontroller to enhance analog functions, support more advanced interfaces, support switching power applications and support functionality for commercial of the shelf (COTS) FPGAs in space.
GR716B is currently in development phase and early prototypes will be available at the end of this year. This paper describes the overall architecture of both devices and details the added functionalities of the GR716B microcontroller.
MICROCONTROLLER APPLICATIONS
Spacecraft subsystem control and monitoring of parameters such as power supply voltages, currents, pressures and temperatures are ideal applications for the GR716A and GR716B LEON3FT microcontroller. Bridges between different communication standards or interface of an equipment towards a higher-level controller or the central On Board Computer (OBC) are also ideal applications for the LEON3FT microcontroller.
The LEON3FT microcontroller can perform advanced data handling to offload any higher-level controller or the central On-Board Computer (OBC). By hiding the data handling details, the transmitting data volume can be reduced. Simplified functionalities as well as timing requirements can be requested to the higher-level controller.
The LEON3FT microcontroller integrates several on- chip data bus standards, such as SpaceWire, CAN, MIL-STD-1553, I2C, SPI, UART and can easily provide data packetization for serial communication using standard protocols. The microcontroller can also efficiently replace FPGAs in accomplishing the above functionalities. Generally, the FPGA implementation is faster. However, much more complexity and flexibility can be captured in the software of a microcontroller, even with limited processing capability. Moreover, the correct use of FPGAs in space applications can be complex. Cost, package size and availability of integrated analog functions can favour the use of a microcontroller versus an FPGA.
A list of possible applications for the GR716A microcontroller is given below:
The development of the GR716B aims at making it possible to add additional applications such as:
This paper describes a small-size and easy to use hybrid DC/DC converter controller with integrated switch. It integrates in one component all the complex functionality required for low power isolated DC/DC converters in space applications, allowing a reduction of size, cost, and design effort.
In a satellite there are tens of low power isolated DC/DC converters that generate the voltage levels needed by control circuitry of the main electronics units. In general, these auxiliary power supplies have to be directly connected to the main bus and, in some cases, directly to the output of the solar array. Due to their low power level, the size and cost are the main performance indicators. However, even though these power supplies are supposed to be simple, they are relatively complicated to implement because most of their building blocks have to be implemented with discrete EEE components.
The described hybrid DC/DC converter controller with integrated switch will reduce the effort of designing custom DC/DC converters to the design of magnetics components, the selection of the rectifier diodes and selection of filtering input and output capacitors.
The proposed hybrid component comprises a power MOSFET, an innovative PWM controller ASIC and few discrete components on ceramic substrate in hermetic package. It combines the advantages of high integration and sophisticated functionality of the ASIC with flexibility of the hybrid, which allows using different semiconductor technologies in the same component and adjusting the component settings according to the particular demand.
The PWM controller ASIC includes an integrated start-up circuit that may be directly connected to the satellite's main power bus, an independent protection that will switch off the PWM controller in case of external or internal failure, fully redundant gate driver, magnetic feedback support and features numerous settings and detection possibilities.
It is able to start directly from the power bus between 15V and 120V without any additional start up voltage required. Due to the integrated low side power transistor, Flyback and Forward converters can be realised with minimum additional components needed for those topologies.
Magnetic feedback support integrated in this controller offers a special advantage of optocoupler-free isolated converter design.
INTRODUCTION
Traditionally, Rad-Hard Permanent Magnet Synchronous Motor (PMSM)/ Brushless DC (BLDC) motor control uses the Field Oriented Control (FOC) method and is implemented using a Field Programmable Grid Array (FPGA) for the digital control portion and the drive and sense power/analog circuits are built using available Rad-Hard discrete or simple integrated circuits. This yields a relatively large size and mass electronic system but drive performance can also be very good (i.e. high speed and high accuracy of the control loop). A solution to optimize the cost and size is to use a highly integrated Analog Front End AFE (e.g. LX7720 Spacecraft Motor Controller with Position Sensing) together with an FPGA. This solution (https://www.microsemi.com/product-directory/space-system-managers/3708-position-motor-controller-ic) lowers the size, mass and cost of the overall implementation and keeps the high speed and high accuracy performance. If, however the very high loop speed is not necessary, it would be desirable to have a smaller, less complex solution. This paper describes what must be implemented to use a high speed rad-hard AFE together with a lower speed rad-hard microprocessor (MCU) for cost and size optimized PMSM drive electronics that runs a sensor-ed FOC control method implemented in software. The AFE + microprocessor solution was successfully prototyped, and measured data is presented.
INTERFACING WITH CURRENT SENSE DELTA SIGMA MODULATORS
When faced with the problem of reading data output of Rad-hard, high precision delta sigma modulators DSMthe classical approach is to use an FPGA and implement a form of low pass decimation filter to convert the single bit delta sigma digital stream to a lower bit rate higher word length (e.g. 16-bit or more) parallel representation suitable for control, data acquisition or Digital Signal Processing DSP applications. Figure 1 shows a canonical implementation of a sinc3 decimation filter that processes data from a second order DSM. Performance of this type of processing is well known in the literature. Additionally, for applications with frequent single event or other glitch-type disturbances designers use a nonlinear filter to make the design more robust.
Figure 1. Canonical implementation of sinc3 decimation filter
LOWER SPEED CONTROL SOLUTION FOR CURRENT SENSE
The traditional approach works well and can yield high frequency of operation but requires the use of an FPGA which could already be used for other aspects of the application. Particularly for motor/actuator control applications, where required speed is limited by the mechanical/inertial properties of the system, the usage of an FPGA could be wasteful. Additionally, software is more of a commodity than hardware/FPGA development so design cycle could be faster if using an MCU. Therefore, it is desirable from a cost optimization perspective to use the current sense sigma delta modulators from a highly integrated AFE like LX7720 together with an MCU like SAMRH71. Because of the low speed/parallel nature of data input path in an MCU, the system needs to decimate the DSM data as quickly and as hardware-free as possible. One possible implementation is to build a two-stage decimation filter, the first stage could use a sinc1 filter and have a simple counter as the first integrator stage. Then, the data is sampled via the counter’s parallel output by the MCU at a low enough first decimation frequency. The second stages of filtering are done in software and executes at the first decimation frequency and, after a second higher order decimation filter, at the output decimation frequency. The single event filter can be inserted between the sinc1 and second decimation filter (sinck) see figure 2. In this example the first counter uses a 4-bit up-down synchronous counter, followed by a decimation by 15 that lowers the data rate from 1-bit at 30Msps to 4-bit at 2Msps. If this is followed by a sinck decimation filter with a decimation by 128 it yields results of 16-bits at 15.6ksps. Simulation results to showcase the resulting performance will be provided including SNR, latency and single even upset (SEU) filter response.
Figure 2. MCU-friendly decimation filter for LX7720 DSM outputs.
DETAILS OF THE MICROPROCESSOR INTERFACE
Luckily SAMRH71 has the capability to implement the above-mentioned external function using an internal timer/counter channel so there is no need for an external counter IC. Use a counter/timer available on the microprocessor. Sampling for decimation is done using a periodic interrupt generated by another timer/counter channel. Figure 3 shows a block diagram of the Motor Control application of LX7720 and SAMRH71.
Figure 3. SAMRH71 and LX7720 MC application block diagram
PROTOTYPING
A prototype was assembled using two evaluation boards for the two chips mentioned before. A traditional motor control software stack was adapted to the acquisition/DSP used for acquiring two/three current channels DSM outputs. Three SAMRH71 Pulse Width Modulation (PWM) resources are used to drive six LX7720 gate drivers. Three of the LX7720 level shifters are used to adapt the 5V position encoder outputs to the MCU IO voltage levels.
RESULTS
The paper will present data captured from the motor control demonstrator application
CONCLUSIONS AND FUTURE WORK
A cost/performance optimized solution using AFE+MCU for radiation hardened motor control was successfully demonstrated. In order to further simplify the application work could be done to integrate the application completely.
When exposed to radiation, semiconductor components exhibit various single-event effect (SEE) and total ionization dose (TID) behavior. Notably, parametric drifts, latch-up and ?functional disruptions? (SEL and SEFI, resp.). These effects have been studied and dealt with in the industry for several decades.
The obvious approach for operating in the space environment, namely the use of radiation-hardened semiconductor processes and components, is not always viable, for technical, economic and possibly other reasons. This statement has become even more important over the last decade, as the demand for launching nano and micro-satellites has increased considerably.
Consequently, there are numerous reasons why it may be advantageous to use generic, off-the-shelf components (COTS) in spacecraft and other high-reliability settings. In short, as long as the operation of the device or component in question can accommodate intermittent loss of function (caused by SEEs) and is therefore not required to have a 100% uptime, then using COTS components in combination with suitable protection against SEL-related over-currents is an effective solution.
A Dynamic Latch-up Current Protection ASIC design project has been carried out by nSilition in collaboration with the Technical Center (ESTEC) of ESA.
As a first step, the device was specified from functional and implementation points of view. Then a feasibility study was carried out in order to select, among several candidates, which CMOS or SOI process could be most suitable platform. A 0.18?m SOI fabrication process was selected and a short list of the devices that will be used on the design was generated.
A test chip was designed initially. One objective was to ascertain the effect of TID on the principal parameters of particular devices. Next, all the functional blocks implemented on the test chip (bandgap, bias circuitry, OTP and OTP programming, charge pump, digital cells, IOs, main switch and its control circuitry), some in multiple versions, were tested against effects due to TID and SEEs. Expected behavior was observed in many cases. The blocks exhibiting suitable behavior were then selected for the design of the LUCA chip.
The LUCA chip contains all blocks necessary to operate the device according to the functional specifications.
A first-order temperature compensated bandgap and together with biasing circuitry provides voltage and current references. These blocks are reused or enhanced from the test chip.
The Power Management Unit (PMU) conditions the supply voltage received on either the VDD or on the VIN pin (two different supply schemes are possible). All the necessary internal supply voltages are partitioned into several supply domains, some at 3.3V, others at 1.8V, typical. The presence of multiple supply domains is part of the on-chip power integrity strategy. It limits the risk that a block with a periodically varying power consumption disturbs the supply of a precise sensor interface or of the ADC. A charge pump, needed to efficiently operate the main switch, is used to create voltages above the VIN voltage.
An internal 10MHz oscillator provides the main clock. An external 10MHz clock can also be used instead (through the CLK pin), in case any residual noise due to the clock of LUCA must be specifically controlled and timed. This may be the case, e.g., when the load being protected by the LUCA is a highly sensitive sensor.
The main switch and all its control and sensing circuitry implement the LUCA?s current control and latch-up current detection functionalities. A ?HIGH/LOW? pin provides a low latency control of the latch-up detection value. This will accommodate applications requiring a fast transition time between a stand-by mode (LOW) and an active mode (HIGH), so that the current limiting protection function does not need to be set for only the maximum active mode current.
Over-voltage and over-temperature circuits are blocks necessary for avoiding potentially destructive conditions. A resistor-based sensing circuity arrangement allows the LUCA to be pre-conditioned at start-up. The value of some external resistors is examined and provides a way to program the threshold of LUCA in case no SPI master is available (standalone mode).
Finally, a telemetry feature is built around a 10b ADC. Using an OBC connected to the SPI interface, various values and status parameters can be read-out at any time: input voltage, load current, temperature, current status of the LUCA, number of remaining automatic restarts after over-current, alert before latching, etc. Once latched (protection triggered), OBC intervention or cycling of the stand-by pin is necessary to restart and power the load again.
Cold spare IOs are used for interfacing all the digital signals to the board. This allows unused/unpowered LUCA devices to be connected to the SPI bus lines and other digital controls. An OTP provides all the necessary trimming and pre-programming in order to achieve satisfactory precision and avoid yield losses due to fabrication process tolerance.
The nSilition?s digital library (tested on the test chip) was made fully synthesizable and automatically place-and-routable for industrial grade digital tools. The layout floorplan was worked out, taking into account package cavity size, thermal considerations, and package parasitic resistances. In particular, the IN-OUT current path constrains the floorplan of the chip.
Finally, the first LUCA prototype chip was taped-out in January, 2020. Packaged samples of first silicon have been received March 2021. First validated engineering samples will be available by August 2021 and tested radiation tolerant devices by the end of 2021.
This work presents the status of the TM/TC MS-ASIC development (telemetry and telecommand mixed-signal application specific integrated circuit) and describes its final implemented features and target applications.
TM/TC MS-ASIC integrates in a single chip solution the functionality of many electrical and electronic components used on spacecraft subsystems. Its main goal is to replace these components, and hence to reduce area and weight of the PCBs (printed circuit boards) implementing these subsystems. Some examples of units located in the spacecraft platform that could benefit from this replacement are RTU/RIU (remote terminal and remote interface units, respectively); additionally, ICU (instrument control unit) used in the instruments of the payload can also profit from this approach. Consequently, the overall spacecraft can be cheaper, lighter and more compact, which is aligned with the emerging trend in the space industry towards reduced-size satellite fleets.
The TM/TC MS-ASIC is implemented with UMC L180 technology, taking advantage of the DARE180U libraries. In fact, the available catalog of DARE180U IO cells was enlarged in the frame of the project (and in the benefit of the DARE users’ community) to cover the cold-spare functionality of the digital communication interface. To reduce risks and development time, the IP of a ΔΣ modulator with suitable performance was reused in this development; additionally, other available IPs were tailored with additional functionalities (low-dropout regulators with over-voltage and over-current protections) or enhanced performances (internal voltage reference). The design has been hardened against radiation effects applying validated techniques in previous projects. The design will be packaged in a CQFP-100.
The function of the TM/TC MS-ASIC is to acquire telemetries and to generate telecommands from sensors and for actuators included in other spacecraft subsystems, such as the propulsion, the AOCS (altitude and orbit control system) or the SADE (Solar Array Drive Electronics). Some examples of these sensors and actuators are thermistors, gauges, magnetometers, star trackers, sun sensors, reaction wheels, control moment gyroscopes, magnetorquers, flow control and latch valves or catalytic bed heaters. To increase the voltage range of the analogue channels, telemetries can be acquired using external sensing networks biased with an internal control. The result is that 54/27 [0; 10] V single ended / [-10; 10] V differential channels limited in band up to 50 kHz can be acquired with 11 ENOB. Telecommands allow bi-level, single pulse, hysteresis, pulse-width modulation and voltage monitoring alarm functionalities with frequencies from 100Hz to 10MHz. Communications interface is implemented as a redundant SPI bus at 20MHz.
The project is currently at the end of the design phase, where extensive mixed-signal post-layout top-level simulations are being carried out to verify the design. Additionally, a system prototype combining in a PCB the test chip of the ΔΣ modulator together with digital core implemented in a PROASIC3 FPFA was validated with excellent results.
This paper presents the measurement circuits and simulation results of Single-Event Transients (SET) in a commercial 65nm CMOS technology. The measurements contain two parts: total SET ionized charge and SET pulse duration. Single transistors of different types and dimensions were implemented as victim devices. Additionally, SET variation due to different supply voltage was investigated. The test chip was tested under a heavy-ion beam with a LET (Linear Energy Transfer) from 1.3 to 62.5 MeV.cm2/mg and a 0-degree to 60-degree incidence angle.
SET ionized charge measurement
The SET ionized charge measurement is based on an adjustable integrator and latch. When the SET ionized charge is generated at one of the victim devices, it will first be integrated by a charge integrator. The integrator feedback consists of 5 binary-weighted capacitors and series switches. By adjusting the feedback capacitor value, the feedback factor and the integrator output can be changed in 31 levels. When the output of the integrator is just enough to flip the latch, the feedback capacitor number is recorded. Then the SET ionized charge amount is converted to the threshold feedback capacitor number.
To calibrate the circuit, a known charge is generated and sent to the integrator. This known charge is injected by a known capacitor with a step signal. The ionized charge measurement circuit can achieve a range of up to 1.5pC with an accuracy of 47fC/step for thin oxide transistor measurement. The measurement range for the thick oxide victim device is up to 4.3pC with an accuracy of 140fC/step.
SET pulse duration measurement
The pulse duration measurement circuits consist of 3 parts: Victim devices, Combiner and Memory Delay Line (MDL). When the SET pulse is generated at one of the victim devices, it will be amplified and picked up by a combiner. Then, this pulse is measured by the MDL. The victim devices are biased by a pair of transistors, one of them is always activated and the other one can be turned on or off to investigate the RC influence on SET pulse duration. To minimize the non-linearity of the measurement, a balanced pulse combiner is built to have the same delay from all input to output. In MDL, the pulse is measured by normalizing it to the number of unit inverter delay T_inv. In this design, a 160-stage MDL is built, which can measure a duration of up to 160x T_inv. Two types of inverter (fast NMOS and fast PMOS) are implemented to minimize the T_inv and improve resolution.
The calibration circuit is implemented to measure the actual Tinv and the delay introduced by the combiner. This is realized by injecting a known pulse to the combiner and MDL. A configurable oscillator is designed to generate this known pulse. The MDL can measure the pulse duration up to 3ns with an accuracy of 18.2ps.
We present the electrical and radiation results (Total Ionizing Dose) of a Pulse Width Modulator (PWM) for space applications implemented in Microchip’s rad-hard 150nm CMOS-SOI process (ATMX150RHA). This PWM is operating with clock signal (externally or internally generated) ranging from 100kHz to 1MHz and its output stage can source and sink high peak currents (up to 2.5A) with capacitive loads up to 10nF, such as the gate of a power MOSFET. Its input voltage range lies within 10V and 14V. This PWM can be used in various DC-DC converter topologies and it has validated in a Buck, in a Boost and in a Push-pull converter. The PWM can be externally adjusted by passive components and most specifically can be altered the overvoltage threshold, the overcurrent threshold, the clocking frequency, the start-up time and the maximum and minimum duty cycle.
The electrical characterization and radiation campaign have been performed from -40°C to 125°C junction temperature, over its input voltage range and for clocking frequencies within 100kHz and 1MHz. The dose rate was 4.35krad/h and the total accumulated dose exceed 300krad. No functional degradation was observed throughout the campaign. The electrical characteristics remained within specifications apart from the leakage current and the output static impedance.
The radiation characterisation results of the GNSS Front-end SY1009 are presented.
The SY1009 is manufactured in the IHP 250nm SiGe process and characterised for SEE and TID radiation behaviour.
The RF front-end, synthesiser and IF signal processing chain has been monitored during the radiation tests. No radiation latch-up and functional interrupts events have been observed. For the TID tests the noise figure and gain of the RF front-end as well as the phase noise of the synthesiser have been monitored. Up to 200krad no deterioration of these performance parameters has been observed. In the paper the GNSS front-end circuit architecture is presented with attained electrical measurements.
The radiation set-up, measurement procedure and environment conditions are described. The measurement results and analysis are communicated together with the lessons learned. The digital radiation hardened library used for the SY1009 in this IHP process is made available to IHP and the space community.
The Space Industry is strongly increasing its commitment to the use of Commercial Off-The Shelf (COTS) components to face and cover the massive production of satellites. Currently, many of the requirements of space applications can only be met by using commercial components. Designing systems with them has the advantage of reducing costs, as they are usually cheap devices that give flexibility to the design and are quick to achieve. On the other hand, the main drawback is the adaptation of these components into the hard conditions of space, such as the extreme temperatures or the radiation environment: knowing the performance under these conditions is critical for establishing the viability of the components [1].
Analog to Digital Converters (ADC) are key elements of any mixed-signal system, connecting the analog world to the digital world. They are always- present devices and their custom design for specific space applications is expensive and time consuming. This has led the use of commercial converters expanding in recent years [2], especially those that have a serial IO interface that facilitates a pin compatibility between different components representing a cost saving for future re-engineering solutions.
This paper presents the work carried out for the performance evaluation of the 16-bit LTC2387IUH (5mmx5mm QFN package) ADC from Linear Technology [3] under the Total Ionization Dose (TID) test [4]. The component was irradiated using a Cobalt60 source, with a dose rate of 210 rad(Si)/h and up to 50krad cumulative dose. Five samples were all pin grounded and five samples were biasing in a static configuration. The paper is focused on the measurements of the two main static parameters of the ADC, the Integral Non-Linearity (INL) and the Differential Non-Linearity (DNL), using the Histogram Method [6]. The dynamic characterization was carried out by the Signal-to-Noise (SNR) evaluation. The paper also gives an overview of the SEE test [5] and its results, where SET (Transient) and SEL (Latch-up) tests were done over four samples.
The LTC2387-16 is a Successive Approximation Register (SAR) ADC with a 15MHz of maximum throughput rate and no-latency operation. It supports a high-speed application using a serial LVDS digital interface with a one-lane or two-lane output modes, depending on the data rate. The converter operates from 5V and 2.5V supplies and has a fully differential ±4.096V input range. No missing codes at 16-bits with a maximum DNL = ±0.8 LSB (typical DNL = ±0.06 LSB). The maximum INL = ±0.8 LSB (typical INL = ±0.15 LSB) and the minimum SNR = 91.2dB. The LTC2387 has an output test pattern that allows to check the digital interface configuration, forcing the ADC data outputs to a known code. This pattern has been used to perform a robust synchronization between the output data and our capture system, seeking to avoid influences on the measured performance due to synchronization errors during the TID test.
Concerning to setup key features, it stands out the manufacture of a custom-made socket integrating the critical capacitors for the SAR typology, the choice of a powerful capture system as the XEM7350 FPGA integration module and the use of an external 1ps phase- jitter clock for the ADC sampling clock. The test instrumentation included the Applicos ATX7006 Automatic Test Equipment (ATE) as the input signal generator: its AWG22 module is a 22-bit 2MHz Arbitrary Waveform Generator with a 50Ohms or <1Ohm output impedance, signal-path filtering possibility, and non-linearity of maximum ±3ppm of range. The input signal generation is fully synchronized to the ADC sampling frequency through the external low-jitter clock.
The paper will include an introduction, a first section describing the setup, the PCB-Capture system, and the evaluation of the electrical parameters, a second section focused on the radiation test and finally the conclusions and future work.
Summary
This paper presents the performance evaluation of the 16-bit LTC2387IUH ADC from Linear Technology under the Total Ionization Dose (TID) and Single Event Effects (SEE) test. The DUT (Device Under Test) is a SAR ADC with a 15MHz of maximum throughput rate and it supports a high-speed application using a serial LVDS digital interface with a one-lane or two-lane output modes. The paper is focus on the measurements of the two main static parameters of the ADC, the Integral Non-Linearity (INL) and the Differential Non-Linearity (DNL). The dynamic characterization was carried out by the Signal-to-Noise (SNR) evaluation.
Key Words / Index Terms:
Analog-to-Digital Converter (ADC), Commercial Off-The Shelf (COTS), Integral-Non-Linearity (INL), Total Ionizing Dose (TID), Single Event Effects (SEE), Radiation Test.
References:
[1] Space product assurance. Commercial Electrical, Electronic and Electromechanical (EEE) components “ECSS-Q-ST-60-13C” Standard. 21 October 2013. URL:https://ecss.nl/standard/ecss-q-st-60-13c-commercial-electrical-electronic-and-electromechanical-eee-components-21-october-2013/
[2] Frederic Tilhac, “Test Methods, Requirements, and Guidelines for Evaluation of TID Radiation Sensitivity of Analog to Digital Convertors (ADC), Digital to Analog Convertor (DAC)”. URL: https://wpo-altertechnology.com/evaluation-tid-radiation-sensitivity-analog-digital-converters-digital-analog-converters/
[3] LTC2387-16, 15Msps SAR ADC datasheet from Linear Technology. URL: https://www.analog.com/media/en/technical-documentation/data-sheets/238716f.pdf
[4] Total Dose Steady-State Irradiation Method “ESCC 22900 Issue 5” URL: http://escies.org/escc-specs/published/22900.pdf
[5] Single Event Effects Test Method and Guidelines, “ESCC 25100” Specification URL: https://escies.org/download/specdraftapppub?id=995
[6] “IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters," in IEEE Std 1241-2010 (Revision of IEEE Std 1241-2000), vol., no., pp.1-139, Jan. 14 2011. doi: 10.1109/IEEESTD.2011.5692956.URL:http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5692956&isnumber=5692955
The needs for increasingly low cost, low space occupancy and
reduced weight in the space industry have made mixed-signal
ASIC integration mandatory.
The aim of the contract was to develop, qualify and deliver
the flight models of the mixed Analog/Digital ASIC, named
ACCORC7 or IM485A for the CODECHAMP Company. It is
a high resolution optical encoder and polarimetric position
sensor.
In a first contract, the CNES and ID MOS selected the mixed-
signal XH035 LV technology to design a set of rad-tolerant
Low Voltage ELT transistors, checked their robustness up to
total ionizing dose of 100Krads and their immunity to the
Single Event Latch-up under heavy ions.
The design of those transistors made it possible to reach the
required radiation level and the characterization of these basic
elements made it possible to have reliable simulation models
in order to secure the result from the first Silicon run.
Once the prototypes were validated by CODECHAMP, ID
MOS launched a production batch for the qualification and
delivery of the flight models.
The European and UK semiconductor industry have been demanding a low cost plastic package solution for microcircuits in low to medium volumes. High volume lines for outsourced assembly and test (OSAT), mostly based in Asia, are dominated by consumer, mobile and automotive applications.
Although assembly of initial prototypes and small quantities into cavity packages can be provided in Europe, this is only cost effective for 10’s of units. Users with low to medium applications such as space, medical, industrial and aerospace are struggling to find assembly at reasonable costs. They are never likely to reach volumes which are attractive to high-volume OSATs. Small batches requiring numerous set-ups and stop-start of production lines make factories very inefficient, in an age where efficiency is critical to their survival and cost structure.
Some users also have compelling technical reasons why even prototypes should be in an over-molded package and that it should be synonymous with production, such as RF, high voltage and thermal characteristics.
In parallel the European space community are rapidly adopting commercial off-the-shelf (COTS) components in plastic packages for use in low earth orbit (LEO) and constellation applications to reduce overall cost, size and weight of the spacecraft when quantities of satellites and missions are increasing exponentially. The use of COTS limits component selection to OEM line cards and there is little or no provision for customised components or emerging technologies (ASICs, MEMS, sensors, compound semiconductors, etc) at a low price point. Also traditional space quality requirements such as traceability, inspections and testing are not usually serviced by COTS providers. To this end the European Space Agency are funding TRL advancements for new technologies including plastic encapsulated devices and looking to produce a version of the ESCC9000 specification to control plastic assembly.
QFN and BGA dominate the semiconductor market with >50% market share, and further analysis by Alter Technology Group shows that European customers are regularly submitting COTS devices in QFN packages devices for upscreening evaluation to ECSS-Q-ST-60-13C. Both QFN and BGA are flexible platforms which can be serviced with common block mold tooling and saw singulation. Soldering techniques and PCB materials are being adapted to cope with leadless packages which were previously undesirable for space applications.
Alter Technology UK are announcing the introduction of a plastic QFN assembly line for low to medium volume applications, from prototype to flight. This presentation will conclude with an overview of the implementation and qualification of the production line, the current status and roadmap.
Alter Technology Group with sites in the United Kingdom, Spain and France are working together with the European Space Agency to evaluate a turnkey supply chain for plastic packages with complete production and validation inside ESA member states.