Speaker
Description
In order to mitigate Single Event Effects (SEEs), a series of simulation methods have been proposed to conduct SEE evaluation. Typically, such simulation studies include 1) transistor simulation and 2) HDL simulation. Transistor simulation tools (e.g. TCAD and SPICE) usually enable simulations based on currents and voltages. They are normally used for small circuits with few transistors due to the high computation effort required for larger circuits. HDL simulations are used for large scale circuits. However, error rates and propagation paths may change due to the physical layouts, which are not covered in the typical HDL simulation. In order to overcome these shortcomings, we have proposed a new scheme where the SEE models of logic gates are built in SPICE simulations and the evaluation is conducted in HDL simulations, so that it may achieve both accuracy and efficiency.
The proposed scheme includes three steps: 1) build SEE behavior models for the employed logic gates from SPICE simulations, 2) rebuild the HDL netlists of the target circuits using digital SEE models and 3) conduct HDL simulations to analyse SEE behaviors in large scale circuits.
In the first step, the transient currents corresponding with the radiation intensity will be injected to the sensitive node to indicate SEEs. The voltage changes at the output ports will be recorded to build SEE behavior models. The generated SEE models contain the information about pulse width, output delay and possibilities of errors. The models can be reused to reduce the simulation time of this scheme.
The second step is to rebuild the netlist and generate simulation files. In order to inject the SEEs in the HDL simulation, the SEE models are represented by HDL tasks, which are bound to specific logic gates. The employed logic gates in the netlist will be replaced by the redesigned modules with SEE tasks. In the HDL simulation, the respective tasks will be executed to inject SEEs. In this scheme, we designed scripts tools using Python to carry out this step automatically.
The final step is to conduct the simulation, analyse the results and optimise the designs. A set of SEE models can be used to create an unified simulation environment. By using the same set of SEE modules, we can quickly evaluate and compare the SEE mitigation performance of different circuits without taking weeks or months to conduct transistor level simulations.
In our work, we conduct the HDL simulation using the ISCAS89 benchmark circuits to verify the proposed scheme. In those circuits, the S27 circuit is the smallest, which contains 15 circuit units and the S28584 circuit is the largest, which contains 11448 circuit units. The simulation results in the circuits indicate the effects of the SET and SEU on circuits from small scale to large scale. The time cost of HDL simulation for ISCAS89 benchmark circuits is elaborated. We can evaluate the time required for the HDL simulation by averaging time costs for each SEE injection.
By using HDL models, one million SEEs can be injected into S27 circuit in just 55 s, while it will take 55 hours in S38584. The time required for SEE simulation increases nearly linearly with the scale of the circuits.
The time required for HSPICE to conduct same experiment is also tested in this paper. Take S27 as example, the time required to conduct 1 ms simulation is less that 1 s in the proposed scheme, while the SPICE will take more than 67000 s. The obtained results exhibit the efficiency of the proposed scheme.
The main contributions of this work can be summarised as follows:
- The proposed SEE simulation scheme provides a rapid, convenient and
universal comparison method to evaluate the designs of circuits in
context of SEEs. By using the identical SEE model set, the SEE
mitigation performance of different circuit designs can be easily
compared under the same simulation environments without considering
complex physical parameters. - The proposed scheme introduces a range of new SEE behaviour models.
Unlike the typical transistor level based SEE behaviour models that
fully rely on low-level currents and voltages simulation inputs, the
proposed SEE models use only high level digital functions in HDL,
therefore it can offer lightweight and fast simulations for large
scale circuits. - The proposed scheme can offer a high level of flexibility. In this
scheme, SPICE simulation and HDL simulation are decoupled. Each step
can be modified to adapt to other methods or tools. It can make full
use of existing models to build simulation environments and be
adapted for various requirements.
This work is supported by the UK Engineering and Physical Sciences Research Council through grants EP/R02572X/1, EP/V034111/1, EP/V000462/1 and EP/P017487/1.
