12–14 Nov 2019
ESA/ESTEC
Europe/Amsterdam timezone

Introduction of Fault-Tolerant Concepts for RISC-V in Space

13 Nov 2019, 15:15
45m
Tennis Hall (Escape Building) (ESA/ESTEC)

Tennis Hall (Escape Building)

ESA/ESTEC

Keplerlaan 1 2201 AZ Noordwijk The Netherlands

Speaker

Mr Jan Andersson (Gaisler)

Description

The presentation will provide an overview of the work performed in the ITI activity Introduction of Fault-Tolerant Concepts for RISC-V in Space Applications. ARIES
Aerospace Research and Innovation in Electronic
Systems) part of Nebrija University (ES), Cobham Gaisler (SE), and QinetiQ Space nv (BE) have evaluated the state of the RISC-V ecosystem, with focus on processor core implementations, and how RISC-V can be applied for use in European space. A processor implementation (Rocket from UC Berkley) was selected and integrated in a system representative of contemporary European space-grade system-on-chip designs, creating a FPGA demonstrator design implemented on Kintex Ultrascale. An end user
evaluation has been performed of the system in order to compare the specific RISC-V system to current LEON implementations from a functional and performance perspective and different solutions to mitigate radiation effects have been evaluated using error injection.

Presentation materials