Speaker
Description
The next generation of the Onboard Computers(OBC) targeting the “New Space Market” will involve the use of Commerical Off The Shelf (COTS) components along with Radiation Tolerant (RT) components. The COTS devices are targeted to provide high performance along with Quality of Service (QoS), high functional integration with a smaller form factor (ideally in a single chip), while the critical and essential functionalities are handled by the RT components. An effective system architecture combining these devices together along with a robust Fault Detection, Isolation and Recovery (FDIR) techniques increases the total availability of the satellite without compromising the core functionalities and performance, offering a cost-effective solution.
EVOLEO Technologies, Germany and AIRBUS Defense and Space, Germany in the frame of the ESA GSTP project CHICS, are developing a full SAVOIR(Space Avionics Open Interface Architecture) compliant and Advanced Data Handling Architecture (ADHA) compatible, radiation tolerant 3U, dual lane OBC, based on the RT Polarfire and Zynq Ultrascale+ Multi Processor System on Chip (MPSoC).
The MPSoC consists of 4 Application Cores (APU), 2 RealTime cores(RPU), Programmable Logic, together with the Polarfire FPGA and multiple memory resources , this infrastructure supports mixed criticality applications typically required for any satellite. The OBC leverages the rich development infrastructure from Microsemi and Xilinx Development platforms, FreeRTOS for RealTime cores, Petalinux for Application cores, Inter Processor communication(IPI) and opensource tools such as XEN Hypervisor for virtualization, ARM TrustZone, Memory and Peripheral protection units controlled by software. These resources aide in developing a comprehensive and reliable software, along with layered FDIR strategy including redundancy, this effectively provides the optimum time and space partitioning required for the essential platform functions and high-performance payload applications. The OBC offers determinism at a system level, allowing flexible processing capabilities such as Symmetric Multiprocessing(SMP) on the APU, resource sharing with RPU, Asymmetric Multiprocessing(AMP) using IPIs, dedicated cache lines to access memory space using hypervisor, leveraging these features will improve the Worst-Case execution time (WCET) and latency of isolated individual functions.
