Speaker
Roberto Romanato
(Thales Alenia Space - Italy)
Description
Nowadays, the continuous increase of the FPGAs complexity requires the adoption of new tools and flows to speed up the design from the modelling phase to the HW prototype. In this presentation, the design flow from high level specifications to the HW validation is proposed, focusing on the use of MATLAB/SIMULINK tools and automatic code generation with SIMULINK HDL-Coder.
