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Description
Infrared lasers have been used in the semiconductor industry for several decades in various applications such as physical debug. Laser injection has been demonstrated as an important tool to study the vulnerability of VLSI circuits to SEE. In particular laser can segment the different vulnerabilities occurring in different layouts throughout the VLSI chip. Despite this, a universal approach to leverage laser for a full-chip reliability assessment of radiation effects has not been realized.
Such an approach that enables the characterization of commercial off-the-shelf (COTS) devices for high reliability applications is highly desirable.
Commercial PIN photodiodes have been studied under neutron irradiation and laser injection. The use of a commercial photodiode as a comparison vehicle is useful because the photodiode provides a large collection volume where a complete charge collection assumption can be made.
The reverse-biased parasitic junctions in CMOS technologies are much smaller than the generous volume of the photodiode. Although the complex geometries and parasitic bipolar effects complicate the picture, a simple collection efficiency factor can be applied to relate the reduced charge collection process in advanced CMOS technologies to that found in a simple PIN photodiode.
In this work we propose a methodology to estimate the intrinsic neutron failure rate for a VLSI circuit in terrestrial applications by characterizing the circuit with ultrafast pulsed laser irradiation and using charge deposition distributions presented elsewhere.
