Speakers
Mr
Constantin Papadas
(ISD)Mr
Laurent Hili
(ESA)Mr
Mohsin Syed
(Airbus D&S)
Description
Currently Airbus DS GmbH and ISD SA are involved in the development of a Demonstrator Chip for the High Performance Data Processor (HPDP), a reprogrammable array processor IP (XPP from the company PACT XPP Technologies), in the STM 65nm radiation hardened technology. The HPDP demonstrator chip is foreseen by ESA as a test-candidate for the first manufacturing run of the radiation hardened STM 65nm process.
The idea behind this prototyping activity is not only to verify the functionality of the HPDP chip design, but also to get accustomed to the chip development flow of the future European deep sub-micron process. The prototyping is planned within the ESA Greek Industry Incentive Scheme. It is estimated that the HPDP prototype chip will be available in Q1 of 2015.
As the STM 65nm process is planned to be made available as a radiation hardened process in the near future, the current exercise enables Airbus DS and ISD to gain experience with using this technology, to get accustomed to the STM development flow, to identify and avoid any hurdles in the future projects. This exercise also assists in identifying any shortcomings of the proposed design methodology for the STM 65nm process.
