15–17 Mar 2016
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
All available presentations have been posted

Highly Reliable System-on-Chip using Dynamically Reconfigurable FPGAs

17 Mar 2016, 15:40
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands

Speaker

Prof. Luca Sterpone (Politecnico di Torino)

Description

Radiation-induced Soft Errors are widely known since the advent of dynamic RAM chips. Reconfigurable FPGA devices based on SRAM configuration memories are extremely sensitive to these effects resulting in an unwelcome change of behavior in digital logic. Indeed, soft errors occur today as a result of radiation from space or even at sea level. Detection, protection and mitigation of soft errors beyond aerospace and defence applications have been widely debated over the last decades. In the present paper we provide a complete design flow illustrating the proper design rules ranging from the synthesis, mapping and physical place and route algorithm tailored to the implementation of high performance and reliable SoCs using dynamic-reconfiguration oriented SRAM-based FPGAs. Radiation experimental results obtained radiation test performed using proton particles demonstrated the goodness of our developed design flow resulting in an overall error cross-section reduction of more than 2 orders of magnitude.

Summary

The VERI-Place tool set applied to Xilinx Kintex-7 devices.

Primary authors

Dr Boyang Du (Politecnico di Torino) Dr Luca Boragno (Politecnico di Torino) Prof. Luca Sterpone (Politecnico di Torino)

Presentation materials