Speaker
Ms
Alexandra Kourfali
(Ghent University / ESA)
Description
SRAM-based logic devices such as FPGAs are susceptible to SEUs and functional interruptions in harsh radiation environments, such as space. Several mitigation techniques have been used in order to sustain the functionality of the design, after SEUs are detected and corrected. However, the majority of these mitigation techniques (e.g. TMR) introduce area overhead in the original design. We propose a methodology that adds an extra layer of reliability to Commercial off-the-shelf (COTS) FPGAs that will allow them to be used safely in space missions. This technique can add an integrated online testing infrastructure in the design, in order to provide extra protection. This infrastructure can detect and correct efficiently possible SEUs occurring in the FPGA’s logic during operating time, by using microreconfiguration. With microreconfiguration the design is dynamically specialised for a subset of its current signals that are susceptible to a SEU. Microreconfigurations are normal FPGA-configurations where some of the bit-values are replaced by Boolean functions of certain signals. An actual FPGA configuration is generated from the microreconfiguration by evaluating these signals. During operating time, when a SEU occurs, the correct bit-values are found by evaluating the boolean functions of the microreconfiguration. These new bit-values can then be loaded into the FPGA configuration memory using partial run-time reconfiguration. This technique can reduce the area overhead after adding the extra functionality for the SEU mitigation technique, as a subset of the signals are replaced by boolean functions, resulting at a new specialised design that is smaller, and in some cases faster, than the original.
Primary author
Ms
Alexandra Kourfali
(Ghent University / ESA)
Co-authors
Mr
David Merodio Codinachs
(ESA)
Prof.
Dirk Stroobandt
(Ghent University)
