SEFUW: SpacE FPGA Users Workshop, 3rd Edition

Prototyping a SOC on RTAX4000D for Solar Orbiter's Low Frequency Receiver.

15 Mar 2016, 11:45

25m

Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Design Experiences

Speaker

Mr Alexis Jeandet (Plasma Physics Laboratory)

Description

Many space instruments using FPGA rely on the RTAX family, from the RTAX-250 to the RTAX-2000D but none of them embed a **RTAX-4000D**. For the first a RTAX-4000D will be onboard the [Solar Orbiter](http://sci.esa.int/solar-orbiter/) spacecraft in the Low Frequency Receiver instrument(**LFR**) developed at the Laboratory of Plasma Physics([LPP](http://www.lpp.fr/)). The LFR is in charge of digitizing the E and B fields below 10kHz and processing them to extract basic parameters from the solar wind. In fact this need more RAM and logical resources than the RTAX2000D can provide, the reason for which the [LPP](http://www.lpp.fr/) decided to choose the RTAX4000D. In this workshop the LFR's FPGA prototyping will be presented from custom solderless socket solution to high level SOC debug and verification.

Presentation materials

Slides

SEFUW3_LFR_A_JEANDET.pdf