Speaker
Mike Wirthlin
(Brigham Young University)
Description
The Xilinx Zynq programmable system-on-chip offers new capabilities for spacecraft systems by integrating two ARM A9 processors along with programmable logic on the same silicon die. Tightly coupling embedded processors with a programmable logic fabric facilitates hybrid computing systems that use the processors for higher-level sequential processing and the programmable logic for parallel computing, low-level I/O, and stream processing’s. A number of CubeSat satellite systems are planning on exploiting this novel architecture. Like all SRAM programmable logic, the FPGA resources on the Zynq processor are susceptible to single-event upsets (SEU). Conventional SEU mitigation techniques such as configuration scrubbing and TMR are necessary for protecting the programmable logic within the Zynq. This presentation will summarize a number of novel techniques for configuration scrubbing using the new PCAP configuration interface. In addition, a hybrid scrubbing system that exploits both the internal scan feature of the 7 series FPGA as well as the PCAP interface will be described.
Primary author
Mike Wirthlin
(Brigham Young University)
