15–17 Mar 2016
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
All available presentations have been posted

The Benefits of Feedback TMR for SEU Tolerance of SRAM FPGA Designs

16 Mar 2016, 12:00
35m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands

Speaker

Mike Wirthlin (Brigham Young University)

Description

Modern SRAM Field Programmable Gate Arrays (FPGAs) provide a large amount of logic, computing, and I/O resources that can be programmed in the field through device configuration. FPGAs are also increasingly including a variety of fixed circuits such as programmable processors and high-speed I/O interfaces to facilitate the development of complex, single-chip programmable systems. Like all semiconductor devices, FPGAs are susceptible to ionizing radiation and experience single-event upsets (SEUs) within the logic configuration memory, user block memory, and user flip-flops. To use SRAM FPGAs reliably in space environments, the negative effects of these SEU must be mitigated. Fortunately, the programmable nature of FPGAs can be exploited to provide SEU mitigation. Programmable resources can be reserved for replication of user circuits to mask circuit failures. Triple Modular Redundancy (TMR) is a popular technique for addressing such SEUs by triplicating circuit resources and adding majority voters. Feedback TMR, a form of TMR that involves insertion of voters in all feedback paths, can be used to provide self-synchronization when circuit resources are repaired. To maximize the benefits of TMR, configuration memory scrubbing is used to repair upsets in the configuration memory during system execution. Configuration scrubbing uses the partial reconfiguration to continuously repair unwanted upsets in the configuration memory before the effects of these upsets overwhelm the TMR mitigation approach. The use of both techniques together has been shown to provide significant improvements in circuit reliability over the use of either technique on its own. Feedback TMR and configuration scrubbing have been applied to a variety of circuits on the Xilinx 7 series FPGA and tested for SEU tolerance using both fault injection and radiation testing. This presentation will summarize the improvements in reliability of a soft LEON3 processor and a B13 ITC'99 benchmark. The fault injection results suggest improvements in mean time to failure of 51x for the LEON3 and 105× for the B13 benchmark. The same designs were tested at the Los Alamos Neutron Science Center (LANCE) and demonstrated improvements in mean-fluence to failure of 47x for the LEON3 and 52x for the B13 benchmark.

Primary author

Mike Wirthlin (Brigham Young University)

Presentation materials