SEFUW: SpacE FPGA Users Workshop, 3rd Edition

Session

Reconfigurability

15 Mar 2016, 16:00

Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Conveners

Reconfigurability

• David Dangla (CNES)

Reconfigurability

• David Merodio Codinachs (ESA)

71. Dyplo: software driven threaded FPGA development using partial reconfiguration techniques

Mr Dirk van den Heuvel (Topic Embedded Products), Ms Inge Rutten (Topic Embedded Systems)

15/03/2016, 16:00

Dyplo is a DYnamic Process LOader, enabling software-like programming capabilities on an FPGA such as threading, dynamic process switching and on-the-fly context switching. This allows seamless integration of FPGA logic in a typical software application without the need of deep FPGA design knowledge. A software API gives you full control over functionality run on the FPGA as well as the data...

45. Fast In-Orbit FPGA Reconfiguration via In-Band TM/TC

Mr Christopher Stender (Fraunhofer Institute for Integrated Circuits IIS)

17/03/2016, 14:00

Flexible payloads often contain one or more reconfigurable FPGAs. In order to use them for various tasks or to quickly deploy new algorithms, a fast FPGA reconfiguration is essential. Unfortunately, satellite telemetry and telecommand (TM/TC) links usually provide only slow data rates for configuration uploads or might not even be available for the payload operator at any time. Thus the upload...