Speaker
Dr
Chen Shen
(Cogenda Pte Ltd)
Description
In this abstract, we report “RunSEU”, a fully-physical
simulation framework for evaluating the SEU cross-section of
CMOS circuits. Applications on the analysis of COTS chips
are presented. Its limitations in engineering applications such
as in-orbit SEU rate prediction or failure mode analysis, and
the extensions required in those cases are discussed.
Primary author
Dr
Chen Shen
(Cogenda Pte Ltd)
Co-author
Mr
Ding Gong
(Ke Jing Da Electronics Ltd)
