Speaker
Mr
Jan Wouters
(Imec)
Description
A radhard space-grade LVDS dual transmitter chip is designed. The functionality includes high input common mode voltage (-4 to 5V), high ESD immunity (8 kV), active failsafe operation (for Rx), and cold spare. To be able to realize this, at transistor level several novel techniques had to be applied; this paper will highlight several of these.
**Rx**: failsafe: a novel architecture is used, in order not to violate an existing patent. The output of a peak detector is compared to the average value of the signal, taken the failsafe detection limit into account through a resistive reference voltage to current to detection voltage transformation. Failsafe is only activated then when the condition exists for a minimum period. Benefit is made of triple well NMOS transistors, as they allow to avoid bulk effect, resulting in an elegant circuit.
**Rx**: the Rx digital output pin is next to the Rx input (prerequisite of the pin diagram, for compatibility reasons). For high CMIR, the LVDS input signal differential voltage is divided by five (by an all-pass filter). Even small parasitic couplings between the output and the input (off and on chip) then potentially result in a system that oscillates, and hence several measures are taken to avoid this: two delays are inserted in the failsafe circuit, filtering input noise&glitches, but such that they do not jeopardize the functional operation: 1. a minimum signal/glitch duration to leave failsafe and 2. a minimum failsafe duration. Receiver hysteresis is implemented in a clever way: the hysteresis is only active when Rx is not in failsafe; again this filters glitches that might appear at the Rx input.
**Also, the Rx (two pins) ESD protection**: 8 kV HBM requires a big protection, which is towards gnd. Hence gnd noise from LVTTL digital output switching is coupled directly into the Rx’s (sensitive) input, and this loop easily might oscillate; this compromised the ESD protection design; solution will be shown.
**Tx**: common mode regulation: classically the common mode is sensed using a differential output resistor. However this results in an extra uncertainty in the LVDS output current. In this design the common mode is sensed by a differential difference amplifier, which does not draw any input current.
**LVTTL digital input**: 5 V input range combined with cold spare (“no VDD”) required the use of some ingenious circuitry to be able to accommodate all possible conditions.
Summary
A radhard space-grade LVDS dual transmitter chip is designed. The functionality includes high input common mode voltage (-4 to 5V), high ESD immunity (8 kV), active failsafe operation (for Rx), and cold spare. To be able to realize this, at transistor level several novel techniques had to be applied; this paper will highlight several of these.
Primary author
Mr
Jan Wouters
(Imec)
Co-authors
Mr
Geert Thys
(IMEC)
Mr
Jørgen Ilstad
(ESA/ESTEC)
Mr
Laurent Berti
(IMEC)
Dr
Richard Jansen
(ESA)
Mr
Stephane Zagrocki
(IMEC)
Mr
Steven Redant
(imec)
Dr
Vesselin Vassilev
(Novorell Ltd)
