# AMICSA 2018

Europe/Brussels
IMEC (Leuven, Belgium)

### IMEC

#### Leuven, Belgium

Kapeldreef 75 3001 Heverlee Belgium
, ,
Description

## 7th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications

### 17th - 20th June 2018

Organized in collaboration with ESA, IMEC and our Sponsors, provides an international forum for the presentation and discussion of recent advances in analogue and mixed-signal VLSI design techniques and technologies for space applications.

• Radiation Effects on analogue and mixed-signal ICs

• Methodologies for Radiation Hardening on analogue circuits at cell-, circuit-, and system design level

• Radiation-hardened technologies for analogue ICs

• Radiation tests of analogue and mixed-signal ICs

• Qualifying and quantifying radiation-hardness of analogue circuits

• Space Applications for analogue and mixed-Signal ICs

• Analogue intellectual property and re-usability of analogue circuits in space

• Needs and Requirements for analogue and mixed-signal ICs in future space missions

• In-orbit Experiences and flight heritage of analogue and mixed-signal ICs
Participants
• Alain Van Esbeen
• Alexandre Rousset
• Alican Kurutepe
• Anton Bychkov
• Antonio Cubeta
• Art Schaldenbrand
• AYDIN SEYMEN
• Bilal Chehab
• Boris Glass
• Bram De Muer
• Charles SELLIER
• Christian Chatry
• Christian Mayer
• Christian Sayer
• Christophe BOUCHERON
• Clement MAURICE
• Daiki Takahashi
• Daniel Gonzalez
• Daniel Walsh
• Danny Lambrichts
• David Juliusson
• David King
• David Levacq
• Diego Vázquez García de la Vega
• Dieter Herrmann
• DIMITRIS MITROVGENIS
• Dirk Van Eester
• Dorian Johnson
• Eran Rotem
• Eric Leduc
• Eric Van Der Heijden
• Erik Ryman
• Ernesto Pun
• Erwann BERLIVET
• Etienne Janssen
• Fernando Martinez
• Florence Malou
• Francesco Parenti
• FRANCISCO MORALES
• Franco Bigongiari
• Frank Henkel
• François Marconcini
• Fredrik Johansson
• Frédéric OUDART
• Geert Thys
• Georgios Evangelopoulos
• Gerard Kennedy
• Giancarlo Franciscatto
• Gilles GASIOT
• Hans-Juergen Sedlmayr
• Hans-Ulrich Zurek
• Hiam Sinno
• Hilde Derdin
• Jacques Michel
• Jan Dielens
• Jan Wouters
• Javier Goyanes
• Jean-Marc BIFFI
• Jens Schmidt
• Jens Verbeeck
• Jesús F. López-Soto
• Jo Van Langendonck
• Joaquín Ceballos
• Jorge Marin
• Jose Moreno-Alvarez
• Joseph Yeomans
• Juan Bevan
• Judith Kroel
• Julien Fleury
• Jörg Ackermann
• king wah wong
• Kostas Makris
• Kris Niederkleine
• Kurt Rentel
• Kurt Stinkens
• Laurent Artola
• Laurent Berti
• Laurent COUTELEAU
• Luc Boschmans
• Marc Fossion
• Markus Mueller
• María Angeles Jalón
• Mathieu Sureau
• Maxence LEVEQUE
• MEHMET SERDAR AYDIN
• Michael Kakoulin
• Michael O'Brien
• Michael Rankins
• Mike WENS
• Moreno Lupi
• Nico Beylemans
• Nicolas Chantier
• Nicolas Puzenat
• Oscar Mansilla
• Ozgur Gursoy
• Ozlem Cangar
• PASCALE CHARPENTIER
• Peter Dirks
• Piet De Moor
• Piet De Pauw
• Remy CHARAVEL
• ROGER ABDOLA
• Romain PILARD
• Sebastian Millner
• Sergey Yakovlev
• Servando Espejo Meana
• Shinji Shibao
• Sonia Vargas-Sierra
• Staf Verhaegen
• Stefaan Decoutere
• stephen rimbault
• Steven Redant
• TAYLAN ÖZONUK
• Teo De Lellis
• Teresa Farris
• Toshitsugu Sakamoto
• Ugo Raia
• Vanessa Monier
• Vesselin Vassilev
• Wojciech Debski
• xavier wiedemann
• Yasuhiro Fukuta
• Ying Cao
Support
• Sunday, 17 June
• 20:00 22:00
Welcome Drink 2h Café Entrepot (Leuven)

### Café Entrepot

#### Leuven

Vaartkom 4 3000 Leuven

http://www.cafeentrepot.be/

• Monday, 18 June
• 09:15 09:45
AMICSA: Introduction
• 09:15
Welcome and Introduction 30m
Speakers: Mr Boris Glass (ESA) , Mr Steven Redant (imec)
• 09:45 11:00

Radiation Effects on analogue and mixed-signal ICs

Convener: Dr Sebastian Millner (Tesat-Spacecom GmbH & Co. KG)
• 09:45
Single Event Effects Analysis in ReadOut Integrated Circuits at Cryogenic Temperatures 25m
Speaker: Mr Laurent Artola (ONERA)
• 10:10
Static Linearity Test for Radiation Effects Characterization of an 18-bit SAR Serial IO COTS ADC: Analog Devices AD7982 25m
This paper reports the testing results of a SuccessiveApproximation-Register (SAR) ADC of 18-bits with Serial Input/Output digital interface. We compare the results of using a standard approach with a new test methodology for SAR static linearity testing. The available test time in between radiation steps is limited in order to avoid annealing. The presented method strongly reduces the amount of output code samples, which implies not only higher test speed but also lower test cost. In high resolution ADCs, performing linearity test using the standard histogram method implies obtaining a large number of samples per code in order to average the measurement noise. This leads to long test time which involve high test costs. Space applications nowadays are trending to the use of COTS devices for cost saving purposes. This is aligned with a reduction in the cost of testing such COTS components. The present work has shown that it is possible to reduce the cost of the linearity test reducing the number of necessary samples. This is done by improving the noise averaging efficiency by using the very accurate input signal information dismissed in the accumulation of the histogram, redistribute the contribution of noise average to all samples and taking care of the high dependence behavior of segmented architectures of some types of high resolution ADCs.
Speaker: Dr Sonia Vargas-Sierra (Alter Technology)
• 10:35
Validation of a High Resolution ADC for Space Applications 25m
Speaker: Mr Kostas Makris (ISD S.A)
• 11:00 11:20
Coffee 20m
• 11:20 12:35
Custom Cell-, Circuit-, and System Design: (1/3)

Custom cell-, circuit-, and system design of ICs for space applications Full custom digital, analogue, or mixed-signal: Front-end, Signal processing, Data converters, Receivers and transmitters, Drivers, or other.

Convener: Mr Marc Fossion (Thales Alenia Space Belgium)
• 11:20
Rad-Hard Telemetry and Telecommand IC suitable for RIU, RTU and ICU Satellite Subsystems 25m
1. Summary/Abstract 2. Introduction 3. Design goals: 3.1. Requirements 3.2. Challenges 4. Architecture analysis: 4.1. Reused IPs 4.2. Block diagram 5. Project milestones 6. Conclusions 7. References
Speaker: Mr Ernesto Pun (ARQUIMEA)
• 11:45
Microchip ATMX150RHA European Mixed Technology for Advanced Designs SAMRH71 25m
Microchip Technology Inc. as a leading provider of microcontrollers for space application design is continuously proposing new devices for the space domain. In addition to an increased power-computing performance, the new generation of microcontrollers integrates more and more advanced analog functions. Use of the ATMX150RHA radiation hardened mixed technology for the development of the new microcontrollers generation allows a high level of system integration. As a reference architecture for mixed system-on-chip, Microchip Technology Inc. is developing the SAMRH71 with integration of ATMX150RHA analog cells in a high performance Cortex M7-based microcontroller. The SAMRH71 embeds a first set of analog functions, mainly focusing the system management features: - linear voltage regulator, including power monitoring features - 32768Hz Internal Oscillator - 32768Hz Crystal Oscillator - 12MHz Internal Oscillator (configurable as 4/8/10/12MHz) - 20MHz Crystal Oscillator To increase the level of integration of such a device, the SAMRH71 embeds 128K of Non Volatile Memory (NVM) and a large set of internal SRAM, thus allowing application running without external memory. The on-chip 128kBytes NVM is built around the ATMX150RHA 32kBytes Flash module . To avoid any electrical influence of the NVM module in the applications that don't require the use of the internal NVM, the SAMRH71 embeds an isolation structure made of ATMX150RHA analog cells. In addition to the isolation of all the IOs of the NVM module, the NVMSWITCHRHA power switch is used to isolate the power supply of the NVM memories from the main SAMRH71 power domains. On the basis of this ATMX150RHA development, Microchip Technology Inc. is working on a derivative of the SAMRH71 reference architecture to provide the market with a smaller device that would integrate more analog cells. This mixed microcontroller will be able to provide advanced functions for control/command applications - 12-bit single-ended / differential multichannel ADC - 12-bit single-ended / differential dual channel DAC - Analog Comparators Taking all the benefits of the IPs developed on the mixed signal ATMX150RHA technology, Microchip Technology Inc. is capable not only to propose a rad-hard technology for ASIC developments, but also to build up advanced controllers that can be disseminated to all the space actors.
Speaker: Hans-Ulrich Zurek (Atmel-Microchip)
• 12:10
Status update on GR716 Rad-Hard Microcontroller For Space Applications 25m
ABSTRACT This paper describes the mixed-signal microcontroller GR716 targeting embedded control applications with hard real-time requirements. Prototype devices are currently beeing tape-out in the activity Microcontroller for embedded space applications, initiated and funded by the European Space Agency (ESA). The presentation and paper will describe the mixed digital and analog architecture, performance of the device. This abstract describes an on-going development where the devices are in the stage to be taped-out BACKGROUND Software based data acquisition, dataprocessing and simple control applications are widely used in spacecraft subsystems. They allow implementation of software based control architectures that provide a higher flexibility and autonomous capabilities versus hardware implementations. For this type of applications, where limited processor performance is required, general purpose microprocessors are usually considered incompatible due to high power consumption, high pin count packages, need of external memories and missing peripherals. Low-end microcontrollers are considered more attractive in many applications such as: - Propulsion system control - Sensor bus control - Robotics applications control - Simple motor control - Power control - Particle detector instrumentation - Radiation environment monitoring - Thermal control - Antenna pointing control - AOCS/GNC (Gyro, IMU, MTM) - RTU control - Simple instrument control - Wireless networking In these kind of applications the microcontroller device should have a relatively low price, a low power consumption, a limited number of pins and must integrate small amount of RAM and most of the I/O peripherals for control and data acquisition (serial I/Fs, GPIO’s, PWM, ADC etc.). The requirements for memory and program length are usually minimal, with no or very simple operating system and low software complexity. MICROCONTROLLER ARCHITECTURE The list below summarizes the specification for the complete system: System Architecture - Fault-tolerant SPARC V8 processor with 32 register windows and reduced instruction set - Double precision IEEE-754 floating point unit - Advanced on-chip debug support unit with trace buffers and statistic unit for software profiling - Memory protection units with 8 zones and individual access control - Single cycle instructions execution and data fetch from tightly coupled memory - Deterministic instruction execution and interrupt latency - Fast context switching (PWRPSR, AWP, Register partitioning, irq mapping, SVT, MVT) - Atomic operations support Memories - 192KiB EDAC protected tightly coupled memory with single cycle access from processor and ATOMIC bit operations. - Embedded ROM with bootloader for initializing and remote access - Dedicated SPI Memory interface with boot ROM capability - I2C memory interface with boot ROM capability - 8-bit SRAM/ROM (FTMCTRL) with support up to 16 MB ROM and 256 MB SRAM - Scrubber with programmable scrub rate for all embedded memories and external PROM/ SRAM and SPI memories System - On-chip voltage regulators for single supply support. Capability to sense core voltage for trimming of the embedded voltage regulator for low power applications - Power-on-reset, Brownout detection and Dual Watch Dog for safe operation. External reset signal generation for reseting companion chip - Crystal oscillator support - PLL for System and SpaceWire clock generation - Low power mode and individual clock gating of functions and peripherals - Temperature and core voltage sensor - External precision voltage reference for precision measurement - Programmable DMA controllers with up to 16 individual channel - Embedded trace and statistics unit for profiling of the system Peripherals - SpaceWire with support for RMAP and Time Distribution Protocol - Redundant MIL-STD-1553B BRM (BC/RT/BM) interface - Multiple CAN 2.0B bus controllers - Six UART ports, with 16-byte FIFO - Two SPI master/slave serial ports - SPI4SPACE. Hardware support for SPI protocol 0,1 and 2 in HW - Two I2C master/slave serial port - PacketWire interface - PWM with up-to 16 channels. PWM clock support upto 200 MHz - Up to 64 General input and outputs (GPIO) with external interrupt capability, pulse generation and sampling - Four single ended Digital to Analog Converters (DAC), 12-bit at 3MS/s - Four differential or eight single ended Analog to Digital Converters (ADC) 11-bit at 200KS/s with programmable pre-amplifier and support for oversampling. Dual sample and hold circuit integrated for simultaneously sampling - External ADC and DAC support up to 16-bit at 1MS/s I/O - Configurable I/O selection matrix with support for mixed signals, internal pull-up/pulldown resistors - LVDS transceivers for SpaceWire or SPI4SPACE - Dedicated SPI boot ROM support for configuration Supply - Single 3.3V±0.3V supply or separate Core Voltage 1.8V±0.18V, I/O voltage 3.3V±0.3V
Speaker: Mr Fredrik Johansson (Cobham Gaisler)
• 12:35 14:00
Lunch 1h 25m
• 14:00 15:40
Evaluation and Qualification

Evaluation and qualification of full custom ICs for space applications

Convener: Dieter Herrmann (DLR)
• 14:00
Re-Thinking Reliability Analysis 25m
Speaker: Mr Art Schaldenbrand (Cadence Design Systems)
• 14:25
Digital Programmable Controller (DPC) : radhard die in low cost plastic package 25m
The presentation covers the lessons learned from introduction of the Digital Programmable Controller ASIC (DPC) into several space products. Full benefit of DPC introduction, like decentralization of equipment management, is currently limited by size & cost of the component, the latter being a key factor for constellations. Alternative packaging trade-offs will be discussed: a non-hermetic BGA type package has been prototyped. Pro & con of the hermetic & non-hermetic options will be discussed including the associated TRL levels.
Speakers: Mr Alain Van Esbeen (Thales Alenia Space Belgium) , Mr Marc Fossion (Thales Alenia Space Belgium)
• 14:50
ESCC Single Phase Qualification 25m
As advanced at previous communications at AMICSA 2012 and 2016, the European Space Components Coordination (ESCC) system has evolved in recent years in order to adapt its methodologies for Qualification. The most recent developments of possible interest for the AMICSA community may be: - the recent approval by the ESCC Policy and Standards Working Group of a so-called Single Phase Qualification (SPQ) approach for microcircuits - the launch of a working group aimed at delivering in 2018 a new scheme for the certification of Assembly and Test Houses (ATH) This paper will describe the principles of implementation SPQ as set in the forthcoming update of ESCC 9000 and the progress in the preparation of the ATH certification scheme. A special focus may be set on new opportunities (new product, new suppliers, a "controlled shortcut" to full Qualification ) which open up now that these developments are underway. The paper will provide as well a summary of the basic requirements applicable to any ESCC Qualification so the AMICSA audience may understand better whether there is anything in it for their activities and products
Speaker: Mr Fernando Martinez (ESA)
• 15:15
Characterization, Screening and Qualification of the MEDA Wind-Sensor ASIC 25m
The paper describes the final characterization results of the MEDA-WS ASIC, which was described in a previous paper in AMICSA-2016. It describes as well the qualification and the screening processes that have been carried out, and the present status of its integration and calibration in the final engineering and flying modules of the wind-sensor instrument. Specific details include to the low-temperature and radiation tests, the final packaging and its qualification implications, as well as some thermal behavior considerations. The paper begins with a brief review of the ASIC description and functionality, as well as the circuit techniques employed for its different circuit blocks and the RHBD techniques used. Although the ASIC fulfils the prescribed specs and accuracy figures, and will be used "as is" in the instruments to be sent to Mars, a few sources of minor accuracy deviations that have been identified will be described together with their eventual future correction in other versions of this or other similar ASICs.
Speaker: Mr Servando Espejo (IMSE-CNM-CSIC / Universidad de Sevilla)
• 15:40 16:00
Coffee 20m
• 16:00 16:50
Custom Cell-, Circuit-, and System Design: (2/3) IMEC

### IMEC

#### Leuven, Belgium

Kapeldreef 75 3001 Heverlee Belgium

Custom cell-, circuit-, and system design of ICs for space applications Full custom digital, analogue, or mixed-signal: Front-end, Signal processing, Data converters, Receivers and transmitters, Drivers, or other.

Convener: Mr Michael Kakoulin (IMEC)
• 16:00
A radhard LVDS chip: transistor level design aspects 25m
A radhard space-grade LVDS dual transmitter chip is designed. The functionality includes high input common mode voltage (-4 to 5V), high ESD immunity (8 kV), active failsafe operation (for Rx), and cold spare. To be able to realize this, at transistor level several novel techniques had to be applied; this paper will highlight several of these. **Rx**: failsafe: a novel architecture is used, in order not to violate an existing patent. The output of a peak detector is compared to the average value of the signal, taken the failsafe detection limit into account through a resistive reference voltage to current to detection voltage transformation. Failsafe is only activated then when the condition exists for a minimum period. Benefit is made of triple well NMOS transistors, as they allow to avoid bulk effect, resulting in an elegant circuit. **Rx**: the Rx digital output pin is next to the Rx input (prerequisite of the pin diagram, for compatibility reasons). For high CMIR, the LVDS input signal differential voltage is divided by five (by an all-pass filter). Even small parasitic couplings between the output and the input (off and on chip) then potentially result in a system that oscillates, and hence several measures are taken to avoid this: two delays are inserted in the failsafe circuit, filtering input noise&glitches, but such that they do not jeopardize the functional operation: 1. a minimum signal/glitch duration to leave failsafe and 2. a minimum failsafe duration. Receiver hysteresis is implemented in a clever way: the hysteresis is only active when Rx is not in failsafe; again this filters glitches that might appear at the Rx input. **Also, the Rx (two pins) ESD protection**: 8 kV HBM requires a big protection, which is towards gnd. Hence gnd noise from LVTTL digital output switching is coupled directly into the Rx’s (sensitive) input, and this loop easily might oscillate; this compromised the ESD protection design; solution will be shown. **Tx**: common mode regulation: classically the common mode is sensed using a differential output resistor. However this results in an extra uncertainty in the LVDS output current. In this design the common mode is sensed by a differential difference amplifier, which does not draw any input current. **LVTTL digital input**: 5 V input range combined with cold spare (“no VDD”) required the use of some ingenious circuitry to be able to accommodate all possible conditions.
Speaker: Mr Jan Wouters (Imec)
• 16:25
Correlators for Interferometric Radiometry in Remote Sensing Applications, A Scaling Perspective 25m
Correlators are extensively used in the field of radio interferometry. Two different types are considered for two applications; autocorrelators for spectrometry and cross-correlators for aperture synthesis. We concentrate on satellite-based applications where power budgets are very restrictive. Several satellites are already employing correlators for interferometric measurements, and future projects are targeting even larger systems in terms of spectral channels in the case of spectrometry and baseline counts in the case of aperture synthesis. Thus, it is important to develop correlators with increasing channel count, either using ASIC technology scaling or by constructing larger systems from several ASICs. Building on earlier ASIC designs, we examine how larger correlator systems can be constructed and the implications this has, in terms of power dissipation, system complexity, and ASIC count. Our findings indicate that, for large systems, having a very high channel count per ASIC is indeed of interest for keeping system complexity and power dissipation down by reducing both ASIC and I/O count, especially for cross-correlators.
Speaker: Mr Erik Ryman (Omnisys Instruments AB)
• 16:50 20:05
AMICSA: Guided Tour and Welcome Reception City Hall (Leuven)

### City Hall

#### Leuven

• 16:50
Leuven Guided Tour 2h 10m Leuven

#### Leuven

• 19:00
Welcome Reception 1h City Hall (Leuven)

### City Hall

#### Leuven

• Tuesday, 19 June
• 09:15 10:00
Keynote Speach: (1/2)
• 09:15
Functional Safety Management in the automotive world and beyond? 45m
ISO 26262 is an automotive standard that was released in November 2011 and has as target to make cars safer. This point is especially important when thinking about the actual trend towards more and more autonomous cars where the amount of safety critical electronics is increasing quickly and where the impact of potential safety critical failures is very high. Wrong decisions taken by the electronic systems can have an important impact on the people inside and outside of the car. The purpose of the standard is, by focusing on systematic and random hardware failures, to help reducing the risk of safety critical malfunctions to an acceptable level. The standard proposes to achieve this through a series of work products and through robust design methods of the system itself and its electronic sub-components. The target of this presentation is to give a quick overview of the purpose and content of the standard and to explain how it relates to semiconductor mixed-signal developments. A general flow will be presented which starts from a safety concept and ends with an architecture that achieves a high diagnostic coverage. The core of the presentation will be dedicated to explaining the challenges to perform a functional safety analysis according to ISO 26262 and present the work products that are recommended by the standard. Also some time will be spent during the presentation to explain the impact of the safety analysis on the architecture of the component under development and to understand when enough has been done to make the device safe.
Speaker: Mr Yves Renard (ON Semiconductor)
• 10:00 10:50
Space Applications: (1/2)

Space applications for analogue and mixed-signal ICs Power handling, distribution and control,instrumentation, actuation, imaging, communication and navigation, or other.

Convener: Mr Jose F. Moreno-Alvarez (Airbus Defence and Space)
• 10:00
SIS20: A CMOS ASIC for Solar Irradiance Sensors in Mars Surface 25m
This paper reports the design and characterization of the ASIC SIS20, planned for an instrument aimed to measure Solar Irradiance on the surface of Mars. It has been designed using the AMS0.35u CMOS technology and with the rad-hard digital library developed at IMSE (Spain). The ASIC is intended for flying with the ExoMars2020 mission. The design was taped out in June2017. Samples are packaged in a 68 pins module. Nowadays, a complete functional testing in the specified range of temperature (-125º C to 50º C) has been carried out for several samples. Figure 3 shows the PCB Test Board. Results are in accordance with the specifications. At this moment, the chips are under the qualification process. Of course, if accepted, the final paper would summarize the results from the lab.
Speaker: Prof. Vázquez Diego (IMSE-CNM-CSIC/University of Seville)
• 10:25
Ultimate earth observation using time delay integration line scan imagers using the CCD-in-CMOS technology 25m
Imec has been developing a combination of CCD and CMOS technology in one process flow. This enables low noise time delay integration (TDI) line scanners including the signal drivers and readout circuit on-chip – which is not possible using CCD imagers. In combination with spectral filters integrated on-chip, this allows high resolution and spectrally resolved earth observation from low orbit (e.g. micro-)satellites. The imec developments, e.g. 7 band CCD-in-CMOS TDI device will be discussed.
Speaker: Dr Piet De Moor (imec)
• 10:50 11:20
Coffee 30m
• 11:20 12:35
Space Applications: (2/2)

Space applications for analogue and mixed-signal ICs Power handling, distribution and control,instrumentation, actuation, imaging, communication and navigation, or other.

Convener: Mr Jörg Ackermann (Integrated Detector Electronics AS)
• 11:20
Channeltron Detector Readout ASIC in 0.35μm HV CMOS for Cold Solar Wind Analysis 25m
The content of the paper focuses on the design of analog front-end readout circuits for Channeltron detectors in 0.35µm CMOS technology for the Cold Solar Wind Analysis.
Speakers: Prof. Hélène TAP (INP-ENSEEIHT LAAS) , Ms king wah wong (IRAP CNRS)
• 11:45
A Fault Tolerant PMAD System Using Radiation Hardened Highly Integrated AFE Integrated Circuits 25m
Speaker: Mathieu Sureau (Microsemi Corp.)
• 12:10
A rad-hard systems-on-chip solution for close-loop motor control 25m
This paper describes the design and implementation of a systems-on-chip solution for close-loop control of remote-handling robotic tools in radiation environment. The original intended application of the development is for remote handling equipment at ITER (a first-of-kind Tokamak fusion nuclear plant). Front-end electronics that located close to sensors and actuators on ITER remote handling systems will face gamma radiation up to 300 Gy/h and a total dose of 1 MGy, and total neutron fluence up to 1015 n/cm2. Hence those electronics are required to be radiation-hardened against total-ionizing-dose (TID) radiation, as well as single-event effects (SEE) caused by neutrons (14 MeV). In order to broaden the application scope of the system, the chips were also designed to be resistant against higher energy particles (e.g., >60 MeV protons and heavy ions). The close-loop motor control system consists of five ASICs:
• A resolver/LVDT to digital converter to read out angle information from a resolver or linear distortion information from a LVDT.
• A resistive bridge sensor signal conditioning ASIC to read out sensors such as RTD, thermocouple, and strain gauge.
• A 24V 10-channel limit switch conditioning ASIC to read the status of limit switches connected to it.
• A 24V 10-channel relay driver ASIC to drive high-side solid-state or mechanical relays.
• A bus communication ASIC to implement the BiSS interface protocol, the SPI master protocol, and the RS485 bus transceiver.
Those ASICs are implemented in two commercial CMOS technologies: a low-voltage 65nm CMOS process and a 0.35µm high-voltage CMOS process. Radiation-hardened-by-design (RHBD) techniques are used in the design of the ASICs to against both TID and SEE, such as:
• use dynamic compensation techniques to mitigate radiation-induced performance drifts;
• use enclosed-layout transistors to reduce radiation-induced leakage currents;
• use guard-rings to mitigate inter-device leakage;
• use guard-rings and of abundant contacts for all wells to mitigate single-event-latchup;
• use triplication and voting for all digital circuits to mitigate single-event-upset;
• use averaging and filtering in analog circuits to reduce single-event-transient.
The potential space applications of the close-loop motor control system could be:
• control of remote handling manipulators and remote operated vehicles;
• speed control of reaction wheels;
• control of electrical propulsion system;
• altitude control of spacecraft and satellites;
• control of electrical valves.
Speaker: Dr Ying Cao (MAGICS Instruments)
• 12:35 14:00
Lunch 1h 25m
• 14:00 16:00
Industrial Presentations
• 14:00
Alter Technology 2h
Speakers: Dr Sonia Vargas-Sierra (Alter Technology) , Mr xavier wiedemann (Alter Technology)
• 14:00
Arquimea 2h
Speakers: Mr Daniel Gonzalez (Arquimea Ingenieria S.L.U) , Mr Ferran Tejada (ARQUIMEA DEUTSCHLAND GmbH)
• 14:00
Atmel/Microchip 2h
Speakers: Mr Erwann BERLIVET (Atmel/Microchip) , Ms PASCALE CHARPENTIER (MICROCHIP Aerospace and Defense Business Unit)
• 14:00
Cobham 2h
Speaker: Teresa Farris (Cobham)
• 14:00
IHP 2h
Speaker: Judith Kroel (x)
• 14:00
imec 2h
• 14:00
Magics Instruments 2h
Speaker: Dr Ying Cao (MAGICS Instruments)
• 14:00
Microsemi 2h
• 14:00
Micross 2h
• 14:00
Microtest 2h
• 14:00
Renesas 2h
Speaker: Mr Oscar Mansilla (Intersil)
• 14:00
Renesas 2h
Speaker: Mr Oscar Mansilla (Intersil)
• 14:00
Serma/HCM Systrel 2h
Speakers: Mr Frédéric OUDART (SERMA Group) , Mr Maxence LEVEQUE (SERMA Group)
• 14:00
Teledyne e2v 2h
Speakers: Ms Lynn Todd (Teledyne e2v) , Dr Romain PILARD (Teledyne e2v)
• 14:00
Thales Alenia Space Belgium 2h
Speakers: Mr Alain Van Esbeen (Thales Alenia Space Belgium) , Mr Marc Fossion (Thales Alenia Space Belgium)
• 14:00 16:00
Poster: Custom Cell-, Circuit-, and System Design
• 14:00
Radiation Hardened Pulse Width Modulator in CMOS-SOI 2h
The aim of this project is to provide Pulse Width Modulator controller solution that will largely simplify Electronic Power Conditioners (EPC) design due to variety of converter topologies that can be realized within one chip and decrease its cost due to integration of more converter elements in one chip. Field of application of our PWM controller can be far greater than EPCs only, ranging from platform to payload units. It can be used in various topologies (Buck, Boost, Buck-Boost, Push-Pull, Flyback and Forward converters) and their synchronous variations. Commonly used regulation control loop is available (voltage mode and current mode). The Pulse Width Modulator ASIC operates with clock signal (externally or internally generated) ranging from 100 kHz to 1 MHz. The internally generated clock is available on an external pin which enables to run other MISAC PWMs for multiphase converters. The clock signal can be shifted by 90, 180 or 270 degrees and can be scaled down up to 8 times. It has one independent voltage reference source (1.25V) and an output pin with an 11mA maximum available current. For PWM signal generation it uses an internal sawtooth generator with its slope trimmable by external components. The Leading edge blanking internal circuit is applied to the current monitoring signal to suppress voltage spikes. The leading edge blanking time, the maximum duty cycle and the minimum duty cycle can be externally configured. Only passive components are needed to for all configurations. PWM output features two 9V to 16V output drivers designed to source and sink high peak currents (up to 2.5A) from capacitive loads, such as the gate of a power MOSFET. The outputs can have four different modes of operation as the needs of the application (single or dual output, alternate, opposite and complimentary). The power supply of the output stage is independent and isolated from the power supply of the rest of the ASIC circuit. Protection circuitry includes a current limiter pulse-by-pulse operation with a 1.25V threshold, a TTL compatible shutdown port, output overvoltage protection circuit and a soft start pin. An under voltage lock-out circuit is used with 600mV hysteresis. The pulse width modulator is implemented in a rad-tolerant 150nm CMOS-SOI process. The ASIC has been radiation-hardened by design techniques (including Triple-Modular- Redundancy, SET filtering, periodic reset with no operation interruption). The project is currently at the start of first samples manufacturing phase.
Speaker: Mr Dimitrios Baramilis (ISD S.A.)
• 14:00
Radiation-Hard X-Band Phase Locked Loop and Transceiver in 0.25 µm SiGe Technology 1h 40m
Speaker: Dr Wojciech Debski (Silicon Radar GmbH)
• 14:00
SEPHY: a 10/100 Ethernet Transceiver for Space Applications 2h
Speaker: Mr Jesús F. López-Soto (Arquimea S.L.U.)
• 14:00 16:00
Poster: Evaluation and Qualification IMEC

### IMEC

#### Leuven, Belgium

Kapeldreef 75 3001 Heverlee Belgium
• 14:00 16:00
Poster: Radiation Testing and Mitigation IMEC

### IMEC

#### Leuven, Belgium

Kapeldreef 75 3001 Heverlee Belgium
• 14:00
Heavy Ion Test Results of Different Analog to Digital Converters 2h
This paper presents the results of heavy-ion induced single event effect (SEE) tests, performed on analog to digital converters (ADC), which are candidates for usage in spacecraft electronics. The experimental data was obtained at Roscosmos Test Facilities during test campaigns in 2017.
Speaker: Mr Sergei Iakovlev (Branch of JSC “URSC” - “ISDE”)
• 14:00
Radiation Tolerant Stochastic Fourier-Transformation Implementation 2h
The Fourier-Transformation is used in numerous applications. The Fast Fourier-Transform (FFT) algorithm allows an efficient hardware implementation. For space applications, radiation (R) is one of the most significant factors to be taken into account, when the reliability of electronic equipment is in the focus. Long-term usage and large temperature variations are present for electronic devices in satellites as well. On circuit level for terrestrial applications the keyword summing up these effects is PVTA, which is the short form for process variations (P), supply voltage variations (V), temperature (T) and aging (A). All these effects (PVTAR) cause bit errors in digital circuits leading to wrong calculations. Since charged particles have the major influence on the accuracy, we will limit ourselves to Single Event Effects (SEE) in the following. Within a fixed-point (FI) representation, such errors have of course the highest impact on the MSB. On the contrary, stochastic computation (SxC) uses bit streams and stores the information in the frequency of a logical 1 or the ratio of logical 1's to 0's. This way all bits have the identical significance and the outlined impacts are expected to have less severe effects on the reliable calculation. This will be demonstrated for the Fourier-Transform. Considering two bit flips, the first one from a 0 to a 1 and the second one vice versa, the actual impact on the FI representation depends on the positions in the digital word, while for the SxC case the errors impacts cancel each other out. A simulation environment is set up to compare both approaches: on the one hand a double precision, scaled fixed-point FFT and on the other hand a stochastic DFT using the two line bipolar representation. Evaluations on the performance are based on the accuracy of the calculated spectrums for a given complex input signal with 64 samples. The FI representation uses 64 bits on the real and 64 bits on the imaginary part for each sample. The SxC system encodes the input signal with four streams (real / imaginary + positive / negative) with 1024 bits each. Both systems are analyzed for different scenarios. Each sample in each case is calculated 100 times and its respective mean is used to compare the systems with each other. In the first place, when no PVTAR effects are present, the FI system can show its higher accuracy and precision compared to the SxC approach; both setups are related to the built in FFT function. The absolute error of the mean of the FI setup is in the order of $10^{-16}$. This value needs to be compared to the order of $10^{-3}$, which was achieved for the SXC approach. Both results prove the afore mentioned expectations and offer good spectral analysis, high accuracy and good precision. Assuming additional scenarios with increased linear energy transfer (LET), process variations, temperature of e.g. 120°C and a supply voltage of 0.8V both setups will need to show its performance. The normalized mean squared error (NMSE) and the signal to noise ratio (SNR) show the PVTAR tolerant characteristic of the SxC approach. Secondly, the aspect of computational complexity is discussed. The stochastic approach has an overall factor of 32 more bits to be stored and processed for calculations. One has to take into account, the more bits are used, the more errors will be present. It is known, that a common N point FFT requires operations of order $O(N log_2 N)$. In more detail the stochastic approach can be reduced to 16N parallel multiplications (logical AND gates) and one large adder (multiplexer with 16 inputs).
Speaker: Mr Kris Niederkleine (Institute of Electrodynamics and Microelectronics - Universität Bremen)
• 14:00
The First SEE Tests Campaign in Turkey at the METU Defocusing Beamline Preliminary Setup 1h 40m
The preliminary setup of the METU Defocusing Beamline was commissioned in December 2017. This beamline, which is at the Turkish Atomic Energy Agency (TAEA) Saraykoy Nuclear Research and Training Center (SANAEM), follows the R&D beamline at the 15-30 MeV proton cyclotron of Proton Accelerator Facility (PAF). The preliminary setup, with two quadrupole magnets provides an irradiation area of 4x6cm with 15% radiation dose uniformity, with a flux of 3.8x10^9 p/cm/s^2. The final setup which will be constructed and commissioned at the end of 2018, will have a adjustable collimator and 3 quadropole magnets, providing users with an irradiation area conforming to the ESA-ESCC 25100 standard, with 10% radiation dose uniformity and a flux menu selectable between 10^6-10^10. The first SEE tests at the preliminary setup were performed with a collaboration of TUBITAK Space Institute. A test card was designed around two units of buffers and the readout was performed using an oscilloscope with frame capture. Two rounds of 25 second DAQ windows were acquired. In this talk, we will first present the METU DBL project and then the results of the SEE tests performed at this new facility.
Speaker: Mr Mehmet Serdar Aydin (METU)
• 14:00 16:00
Poster: Space Applications
Convener: Mr David Levacq (ESA)
• 14:00
Speakers: Mr Dimitris Mitrovgenis (Senior IC Designer) , Mr Theodoros Athanasopoulos (Technical Director)
• 14:00
Multi-Channel Preamplifier IC for IR-Sensor and FPA Readout 2h
We present the IDE1060, an integrated circuit (IC) with 34 preamplifiers for reading out infrared (IR) sensors and focal plane imaging arrays (FPA). We designed the circuit under contract with the European Southern Observatory (ESO) where the device shall be used with typical large format astronomical IR sensors, e.g., Raytheon Aquarius and Teledyne HAWAII-2RG. The IDE1060 is intended to replace the fast readout amplifiers described in Ref. [1]. The circuit is designed for extreme operational environmental conditions: cryogenic to room temperature, latch-up immunity and high energy threshold for single event upsets from ionizing radiation. Based on the design methods we expect the circuit to be suitable for space-borne astronomical instruments as well. The device is manufactured in Q1 2018 and characterization is planned for the remainder of the year.
Speaker: Mr Jörg Ackermann (Integrated Detector Electronics AS)
• 15:00 16:00
Coffee 1h
• 16:00 17:15
Custom Cell-, Circuit-, and System Design: (3/3) IMEC

### IMEC

#### Leuven, Belgium

Kapeldreef 75 3001 Heverlee Belgium

Custom cell-, circuit-, and system design of ICs for space applications Full custom digital, analogue, or mixed-signal: Front-end, Signal processing, Data converters, Receivers and transmitters, Drivers, or other.

Convener: Mrs Florence Malou (CNES)
• 16:00
Prototype of a multi-mode C-Band capable 12-bit 1.5/3/6 GSps Quad ADC in flip-chip non-hermetic technology 25m
Teledyne e2v has developed a new ADC to meet the high dynamic range as well as channel integration requirements of telecommunications payloads. It is a quad channel single core 12bit 1.5 GSPS designed by Teledyne e2v on ST Microelectronics BiCMOS9 technology which features 0.13µm CMOS and SiGeC NPN HBT bipolar technology (Ft/Fmax = 166/175GHz). The built-in Cross Point Switch (CPS) allows a multi-mode operation with the possibility to interleave the four independent cores in order to reach higher sampling rates. In 4-channel operation mode, the four cores can sample, in phase, four independent inputs. In 2-channel operating mode, the cores are interleaved by 2 in order to reach 3 GSps sampling rate on each one of two inputs. In 1-channel operating mode, a single input is propagated to each one of the four cores which are interleaved by 4 in order to reach a sampling rate of 6 GSps. The -3dB input bandwidth is more than 5 GHz in order to be able to directly sample signals in the C-band (4-8 GHz). This high flexibility enables the access to microwave-frequency signals with up to 3 GHz of instantaneous bandwidth. It also enables the qualification of a single component which is capable to meet a variety of application needs from single to multi-channels, from baseband to more than 5 GHz of input bandwidth. The device is built in a non-hermetic flip-chip package using HiTCE (High Coefficient of Thermal Expansion) glass ceramic material in order to reach optimized RF performance and higher pin density. The new high reliability European flip-chip assembly line deployed by Teledyne e2v is being used for this device. Teledyne e2v is a leader of the flip-chip assembly Working Group which has introduced flip-chip assembly in the ESCC Generic Specification n°9000 in 2016. The paper will develop the following aspects: Target noise power ratio performance in multiple Nyquist zones Cross talk isolation in excess of 70dB at 2.4GHz Chosen ADC architecture, including built-in Cross-Point Switch for multimode operation Introduction of chained ADC synchronization for antenna arrays System benefits of C-Band high dynamic range digitization Mitigation of radiation effects on ST Microelectronics BiCMOS9 technology. Choice of package technology: RF performance and 2nd level reliability Challenges of Flip-Chip assembly at space level.
Speaker: Dr Romain PILARD (Teledyne e2v)
• 16:25
Atom-Switch FPGA for IoT Sensing System Application 25m
Speaker: Dr Toshitsugu Sakamoto (NEC Corporation)
• 16:50
Robust CMOS time-based sensor interfaces for space applications 25m
The harsh environment of space mission applications is at the same time a growing field and a challenging playground for electronic sensor systems. The need of accurate and reliable information about several parameters such as structure sanity, turbine combustion and fuel tank state, among many others, requires sensor systems to be placed *in situ*. Thus, robust, reliable and accurate sensing systems are required to operate in hostile environments under extreme temperature, pressure, humidity, vibration and radiation conditions. Several harsh-environment-compatible features have already been demonstrated using the BBPLL-based CMOS sensor interface architecture for both capacitive and resistive sensors. The main property of this time-based architecture is the robustness provided by the direct sensor-to-digital conversion, by means of the time-domain representation of the sensor data. Since the signal does not need to be amplified before digitization, area- and power-consuming analog blocks and their nonideal effects are bypassed. Additionally, its oversampling operation provides enough redundancy to filter out in the digital domain corrupted data produced by analog transient effects such as single-event radiation effects. Another feature is the highly-digital implementation, compatible with digitally-assisted techniques such as time-based signal chopping and differential-path tuning which can improve the resolution and accuracy performance of the system by reducing the effect of DC and low-frequency perturbations. These techniques can be configured to implement simple built-in self-test strategies that can provide information about the state of the circuit and feed it back for compensation. In such way, smart system-level operation can be achieved by driving capabilities at local level, for example in the case of wireless sensor networks. This paper presents an overview of the robustness properties of time-based sensor interfaces demonstrated until now in CMOS technologies, which indicate a good compatibility with space applications. Furthermore, the presented demonstrators constitute a good example on how CMOS technologies are used as a low-cost prototyping platform to explore space solutions to be further implemented in more expensive technologies used in space applications. Two study cases are discussed. The first demonstrator is a BBPLL-based capacitive sensor interface which can achieve 14-bit resolution. The interface uses time-domain chopping as the main source of compensation between the VCOs mismatch and low-frequency noise. It shows high linearity operation, which simplifies calibration by reducing the number of calibration data points needed. The second interface is a fully-differential BBPLL-based resistive-bridge sensor interface. It provides a very high drift resilience by combining different digitally-assisted techniques. A simple online monitoring technique allows to compensate for sources of drift other than temperature, such as package strain variations and circuit component degradation. Thus, this interface is suited for very harsh environments. The target temperatures in this work, even if far from the maximum required values for space applications, demonstrate the validity of the subjacent principles. The examples discussed have medium-to-high resolution, consume low power and a have a small footprint. This implies low-weight implementations since low volumes are needed for the chip and the batteries. This work constitutes a step towards robust, accurate, light/compact and smart wireless sensor systems which can collect and process high fidelity data locally in nowadays’ space missions.
Speaker: Mr Jorge Marin (KU Leuven)
• 19:00 21:00
AMICSA: Conference Dinner Faculty Club (Leuven)

### Faculty Club

#### Leuven

Groot Begijnhof 14 3000 Leuven Tel : 016/32.95.00
• Wednesday, 20 June
• 09:00 09:45
Keynote Speach: (2/2) IMEC

### IMEC

#### Leuven, Belgium

Kapeldreef 75 3001 Heverlee Belgium
• 09:00
Perspectives for Disruptive GaN Power Device Technology 45m
Today, GaN-on-Si is accepted as a break-through power electronics technology. The favorable materials characteristics and the enhancement mode lateral HEMT device architecture have led to disruptive device performance. Issues with trapping effects and reliability that plagued early versions of the technology have been addressed and first products are in the market. While we will see through further evolutionary improvements the maturity of today’s GaN-on-Si technology further increase with fast pace, research is focused on substrate technology, novel device architectures, application specific customization and higher levels of integration. To unlock the full potential of the fast switching power devices, monolithic integration of a half-bridge, co-integration of the GaN drivers, and free-wheeling diodes offer a way to reduce parasitic inductances, while on-chip temperature sensors and protection circuits increase the robustness. Such power GaN-IC’s pave the way for unprecedented compact high-end power systems.
Speaker: Stefaan Decoutere (IMEC)
• 09:45 11:00

### IMEC

#### Leuven, Belgium

Radiation-hardened technologies for analogue and mixed-signal ICs

Convener: Dr Constantin Papadas (ISD SA)
• 09:45
Microchip ATMX150RHA Rad-Hard CMOS 150nm cell-based ASIC family Radiation Characterization Test Report Total Dose (TID) and Single Event Effects (SEE) 25m
Speaker: Mr eric leduc (1967)
• 10:10
DARE180U platform improvements in release 5.6 25m
Speaker: Mr Giancarlo Franciscatto (imec)
• 10:35
The Design Against Radiation Effects (DARE) design platform for TSMC 65nm process. 25m
Speaker: Mr Michael Kakoulin (IMEC)
• 11:00 11:20
Coffee 20m
• 11:20 12:35

### IMEC

#### Leuven, Belgium

Kapeldreef 75 3001 Heverlee Belgium

Radiation-hardened technologies for analogue and mixed-signal ICs

Convener: Mr Franco Bigongiari (SITAEL S.p.A:)
• 11:20
Overview of ST Space Qualification in 28nm-FDSOI 25m
The good intrinsic radiation resilience of the 28nm-FDSOI technology was demonstrated and reported by ST in 2014. The full space compliance of the ST industrial design platform has additionally required a wide deployment in terms of proprietary radiation modeling, design mitigation and extensive testing against protons, heavy ions and gamma rays. This overview presents 100 new space IPs in 28nm-FDSOI (std cells, memories, serdes, converters, PLLs, analog IPs, sensors) whose space qualifications are being completed by ST thru 25 existing testchips. Last, but not least, the concurrent design of new best-in-class space SoC (ARM-R52, FPGA) is also illustrated in ST 28nm-FDSOI.
Speaker: Dr Gilles Gasiot (ST Radiation Team Crolles)
• 11:45
ATMX150RHA Circuit Design Platform 25m IMEC

### IMEC

#### Leuven, Belgium

Kapeldreef 75 3001 Heverlee Belgium
Microchip Technology Inc. is a leading provider of microcontroller and analog semiconductors, providing 150nm SOI technology (ATMX150RHA) for space product design. We manage full space product supply chain till qualified packaged products according to agencies standards, including foundry and ASIC design services. Building on ATC18RHA heritage, the ATMX150RHA design platform extend possibilities from digital to analog and mixed signal circuit design. To ease SoC design, Microchip provide qualified radiation hardened libraries of IOs, standard cells and analog IPs. Qualified domain extension to analog macros, use a strategy based on enhanced Standard Evaluation Circuit and dedicated test vehicle. Our enhanced Standard Evaluation Circuit contains digital requirements to qualify our technology up to 22M gates, analog monitoring cells, and a set of representative analog IPs. Our test vehicles are used to characterize analog IPs in a standalone mode, for electrical characteristics, radiation robustness and life time. A first set of IPs have been design and successfully qualified. These IPs are: - a linear voltage regulator, including power monitoring features - an analog multiplexer - an internal oscillator - a bandgap voltage reference We will present our results. In order to support analog or digital on top design flows, we provide packages containing libraries (IOs, standard cells and IPs). For digital design flow, physical, timing and behavioral models are provided. For analog design flow, we provide IOs and standard layouts and schematics. Regarding IPs, a black box layout and encrypted spice netlist are provided to allow integration and simulation
Speaker: Mr Erwann BERLIVET (Atmel/Microchip)
• 12:10
DARE SET Simulation Flow Integrated in Virtuoso ADE L/XL Design Environment 25m IMEC

### IMEC

#### Leuven, Belgium

Kapeldreef 75 3001 Heverlee Belgium
One of the important steps when doing radiation hardening by design for mixed-signal and analog blocks is simulation of SET events. It is needed to find the SET sensitive nodes in a design and then adapt the design to bring the SET hardness in compliance with the specification. In order for an analog designer to do this efficiently the tools used should be integrated in the normal analog design flow. It should be flexible enough to screen for sensitive nodes in a design and later on focus on certain nodes. In analog design the timing of an event is important as a strike often only generates a non-compliant SET on the output when the circuit is in a certain state or transition. The timing may be dependent on the simulation corner and ideally the testbench should not need to be changed for this dependence. Additionally it should be avoided that a certain circuit has to be adapted to be able to inject an SET pulse in any node in its hierarchy. Up to now for DARE development at imec a SET_STRIKER cell combined with a deepprobe cell was used. The SET_STRIKER is a model for the SET pulse generated by a single strike of a particle. The purpose of the deepprobe – included in the latest releases of analogLib included in Virtuoso IC – is to allow to inject in any node in the hierarchy of the circuit without the need of adaptions in the circuit. Alternatively, an ocean script is used to inject SET pulses in all nodes in a design. With the extensive use of these tools possible improvements were indentified: * The single strike generated by one SET_STRIKER meant that for each event that one wanted to include in the simulation a separate instance had to be included in the testbench and the timing between the events had to be set manually. Each of the SET_STRIKERs had to be accompanied with its own deepprobe to inject in the right location. If one wants to do a simulation on only a subset of the nodes all the unwanted ones has to be disabled manually. * The deepprobe only connected to one node so it was assumed that the injection always happened with the other end of the SET_STRIKER connected to either the ground or the supply of the circuit. This is most of the time the case as most of the time the bulk of a transistor is connected to one of these nets. When this is not the case two deepprobes should be used but that may be overlooked when setting up the test bench. * The ocean script is mainly used for checking of standard cells and does not have the right capability to properly time the events as needed for analog radiation hardening by design and is not integrated in the analog design flow. In the DARE65 project (contract no. 4000117214/16/NL/LF) then the SET simulation flow was improved based on the identified shortcomings: * SET_STRIKER was extended with a SET_STRIKER_PERIOD and a SET_STRIKER_TRIG cell. These two cells allow to generate several SET pulses. The first cell generates events with a periodic repetition and the second one events triggered by an input signal. * A dual deepprobe was made that connects to two nodes in the circuits. It uses a list of node pairs and can switch between the pairs during the simulation. Again two variants are available, one that switches periodically and one that switches triggered by external signal. * A support window is available to get a list of all sensitive nodes in the circuit under test and select a subset of the nodes for simulation. This set can then be saved. It also allows to highlight the nets and nodes of the selected pairs. * A second support window is available that allow to look up the nodes to which an SET pulse was injected in the circuit under test. With these improvements implemented the analog designer now has a flexible tool set that allows to simulate all needed events with a single instance of a deepprobe and an SET pulse generator with the needed flexibility and efficiency to use it for SET hardness screening and problem fixing.
Speaker: Mr Staf Verhaegen (imec)
• 12:35 14:00
Lunch 1h 25m
• 14:00 15:15

Radiation-hardened technologies for analogue and mixed-signal ICs

Convener: Mr Frank Henkel (IMST)
• 14:00
ESS180RH: An 180nm digital library addressing Single Event Latch-up based on X-FAB XH018 25m
European Sensor Systems S.A is a global developer and manufacturer of high quality sensors based on MEMS. In the course of an ESA activity, titled “Space Qualified Family of MEMS Pressure Modules for Satellite Applications”, European Sensor Systems S.A is developing a custom radiation-hardened capacitive sensor signal conditioning ASIC for interfacing with the MEMS pressure sensors. The ASIC is built using X-FAB XH018 Process Design Kit, a 0.18 micron Modular Mixed Signal HV CMOS Technology. This paper presents a detailed procedure for radiation mitigation against Single Event Latch-up (SEL) effects at physical implementation level and the results of the irradiation campaign at UCL cyclotron. A SEL is the result of the triggering of a parasitic thyristor (PNPN or NPNP structures) mainly existing in CMOS circuits. When it occurs, a high current flows from voltage supply to ground and if the power supply is maintained, the device can be destroyed by thermal effect. The mechanism is well documented in the literature [1]. In the analog part, preventing latch-up from occurring was done by reducing the gain of the two parasitic transistors by increasing the distance between the two parasitic complementary transistors where possible, reducing parasitic well and substrate resistors by using low resistance ground contacts and by surrounding MOS transistors with guard rings. In practice, all PMOS devices have been enclosed by N-type guard rings and all the NMOS devices have been enclosed by P-type guard rings. For the digital part a SEL immune library was required. At that time, the IMEC DARE180X [2] was under development and not fully tested, so it was decided to build a custom on-site library immune to SEL allowing full control of synthesis and place and route procedures. The library ESS180RH consisting of digital cells has been designed and characterized in house to enhance radiation tolerance. It is a 3.3V junction isolated, low power library and contains combinational (logic gates), sequential (scan flip-flops) and special cells (layout fillers, antenna protection cells, level shifters). In the layout the triple well NMOS and PMOS devices have been surrounded by P-type and N-type guard rings respectively. The increase of the layout area compared to a conventional cell varies from 2x to 4x. More specifically, after the layout of each cell is finished, a Library Exchange Format (LEF) file is generated, which includes design rules and abstract information about the cells. An RC parasitic extraction is performed in order to obtain an extracted netlist for analog simulations. The purpose of this step is to perform the modelling of interconnects (resistive and capacitive parasitics) and capturing of the Layout Dependent Effects (LDE) that affect the transistor characteristics and depend on layout placement. The extracted netlist of each cell is then used to perform analog simulations. The output of this step is the creation of the Liberty™ library format, which is an ASCII representation of the timing and power parameters associated with each cell. The timing and power parameters are obtained by simulating the cells under a variety of conditions (Process Voltage Temperature) corners and are used for static timing analysis and power analysis. It contains timing models and data to calculate I/O delay paths, timing check values, interconnect delays. The structure of the .lib file is quite complex. The detailed description of the .lib file and the derivation of the timings is out of the scope of this document. Instead some important aspects are described here for the combinational and sequential cells. The timing characterization is performed using a two-dimensional timing model where the two independent axis variable are input slew and output load capacitance. This means that a two-dimensional matrix is created for each metric, where each row corresponds to the Input Slew and each column to the Output load capacitance. The ASIC was manufactured and tested for SEL in the UCL cyclotron accelerator facility at worst case conditions (maximum voltage supply 3.6V, 85 °C). The ASIC exhibited immunity when the heavy ions shown in Table 1 were used as irradiation sources. ![enter image description here][1] To conclude with, preventing SEL to occur demanded interventions at physical level. For the analog part the solution is quite common. As far as the digital part is concerned, a new 3.3V digital library ESS180RH has been created based on custom layout, parasitic extraction, simulation of the cells and generation of appropriate timing and layout files. The procedure for the creation of the library is fully automated and script-based once the layout is completed and can be easily applied to other foundries or PDK flavors. 1. European Cooperation for Space Standardization, Space product assurance, Techniques for radiation effects mitigation in ASICs and FPGAs handbook, ECSS-Q-HB-60-02A, September 2016 2. IMEC, DARE180X, http://dare.imec-int.com/en/technologies/dare180x [Accessed on 10/2/2018] [1]: https://i.imgur.com/QTwQScr.png
Speakers: Mr Dimitris Mitrovgenis (Senior IC Designer) , Mr Theodoros Athanassopoulos (Technical Director)
• 14:25
Mixed-Signal Test Vehicle in Microchip Atmel ATMX150RHA 25m
Introduction ------------ A test vehicle has been designed and tested by Airbus Defence and Space and CNES to evaluate the ATMX150RHA technology from Atmel Microchip. The design and test have been fully subcontracted to Weeroc. A 16-bit 10MSPS dual DAC and a series of analogue switch compose the main core of this test vehicle. On top of these main features, a selection of high voltage transistors, capacitors and resistors from the analogue library has been added for further total dose irradiation test. Fast LVDS transmitter and receiver from Atmel new 3.3V I/Os library have been added to characterize these new I/Os. 16-bit DAC Description ---------------------- The 16-bit DAC has been specified by Airbus Defence and Space. The main requirements are 16-bit parallel input, differential current output, embedded trimmable current reference and multiplying DAC capability, from 4 to 12 MSPS. The chosen architecture based on these requirement has been a mixed of binary and thermometer current steering DAC. The binary part is driving the 12 less significant bits while the thermometer structure drives the 4 most significant bits. A large array of transistor composes the main current source of the DAC. This array distributes semi randomly the current to any of the output of this DAC. Dummy transistor structure allows mismatch reduction in the current sources. The size of the array has been kept small to allow DAC multiplication capability at rather high frequency. A trade-off between output non-linearity and switching speed is required which translates into optimising the transistor mismatch and parasitic capacitance reduction. The current switching part is composed of latency-controlled buffer and binary-to-thermometer converter followed by an array of scaled latches. The latches control injected-charge compensated switches allowing to draw current in positive or negative branch of the analogue output. Voltage and current references are provided by a bandgap structure and a programmable current source. The DAC is biased in 1.8V. Internal voltage regulators allow 3.3V to 1.8V conversion. Architecture and measured performances will be presented in this paper. Fast Analogue Switch -------------------- The fast analogue CMOS switch has been specified to have a 500MHz bandwidth with a below 20 Ohm Ron. The switch must be 5V compatible and shall have a transition time below 20ns. It has been designed to be both 3.3V and 5V compatible with a 1.8V or 3.3V control signal. Several configuration of that switch including a T structure has been embedded and tested in the test vehicle. Measurement results on that switch will be presented in the paper. Conclusion ---------- This paper is aimed to present silicon measurement of a first test vehicle in a promising mixed signal technology widely used in automotive industry and qualified for space application. That test vehicle is a first step towards a unified and qualified European analogue IP library. Promising results and future development plan will be presented.
Speaker: Mr Julien Fleury (Weeroc)
• 14:50
DARE180U New Analog IPs 25m