Speaker
Mr
Giancarlo Franciscatto
(imec)
Description
DARE180U, formerly named DARE180, is a mixed-signal ASIC design platform intended for radiation hardened applications up to 1 Mrad implemented in the commercial UMC L180 MM/RF 1.8V/3.3V, Single Poly 6 Metal (1P6M), P-Sub/Twin-Well CMOS technology. Over the years, DARE180U has been adopted by many partners around the world and it has recently obtained maximum TLR-9 status with chips launched in commercial planetary missions.
Release 5.6 is a major step in the DARE180U solution as it brings together extensive knowledge acquired in the past years from several application designs and test chips. This paper discusses the updates in this release which includes general improvements made to the platform as well as new additions and enhancements on existing libraries and IP.
General improvements include the support to full-custom black-box design and the use of a new ELT simulation model that has been fine-tuned using comprehensive test results from the DARE+ project supported by the European Space Agency.
DARE180U CORE library has been fully reviewed to optimize sensitive area of critical nodes and to improve electrical behavior around ELTs. More efficient layout techniques have also been employed to reduce area in most cells and to enable better top-level routing. As well, characterization data using the new fine-tuned ELT models has been generated to deliver more accurate timing results.
I/O libraries have been completely rearranged with all digital and analog I/O cells being included in a single library whereas bond pad cells are provided in a separate library. The new I/O cell library has been largely extended with new analog cells, breakers and supply cells that enables different implementations of 1.8V and 3.3V mixed-signal domains in a single I/O ring. As well, several modifications have been done on layouts to improve ESD behavior and electromigration. The new bond pad cell library includes an entirely new set of structures featuring several pad opening sizes for different pitch requirements as well as special double bond pad cells to be used with DARE180U-specific IP.
DARE180U IP, such as LVDS and PLL, have also been updated to attend new requirements and to fix existing issues reported in previous application chips. On top of these, new IP implemented at imec have been added to the platform such as ADC, DAC, bandgap, LDO and ring oscillators.
In this release, the DARE180U SRAM compiler has been revised to fix known bugs and to deliver more accurate characterization data based on new ELT models. This compiler features the implementation of both single-port and dual-port SRAM blocks with possible sizes ranging from 256 bits to 256 Kbits. All generated instances are in line with the TID specifications of the DARE180U libraries and MBU insensitivity can be achieved by specifying proper bit interleaving in the compiler and employing external error detection and correction circuits.
Primary author
Mr
Giancarlo Franciscatto
(imec)
Co-authors
Mr
Geert Thys
(imec)
Mr
Laurent Berti
(IMEC)
Mr
Staf Verhaegen
(imec)
