AMICSA 2018

A rad-hard signal conditioning ASIC for space grade transducers

19 Jun 2018, 14:00

2h

Poster Radiation-hardened technologies for analogue and mixed-signal ICs Poster

Speakers

Mr Dimitris Mitrovgenis (Senior IC Designer)Mr Theodoros Athanasopoulos (Technical Director)

Description

European Sensor Systems S.A is a global developer and manufacturer of high quality sensors based on MEMS. In the course of an ESA activity, titled “Space Qualified Family of MEMS Pressure Modules for Satellite Applications”, European Sensor Systems S.A is developing a custom radiation-hardened capacitive sensor signal conditioning ASIC for interfacing with the MEMS pressure sensors. The ASIC is built using X-FAB XH018 Process Design Kit, a 0.18 micron Modular Mixed Signal High-Voltage CMOS Technology. This paper presents the approach followed to solve the issues identified during the test campaign of the first revision and were mainly related to irradiation effects at the output stage of the ASIC as well as early characterization results. To start with, the ASIC is capable of interfacing both single and differential sensor architectures. The range of the full-scale input capacitance changes up to ±5.6pF, with a base capacitance of up to 40pF in order to cover the application requirements for pressure ranges of 7, 22, 150, 310 bara. Sensor capacitance variations can be compensated by an on-chip trimmable capacitor bank. The Capacitance-to-Digital Converter combines the Capacitance-to-Voltage converter with a second order ΣΔ modulator and a decimation filter to produce a high resolution output with a programmable update rate. It also incorporates a temperature sensor. In order to reduce the effect of low frequency noise and mitigate the problem of amplifier offset due to TID irradiation, a circuit-level approach has been used at the sensitive core blocks. An operational amplifier with chopper stabilization has been used for the capacitance-to-voltage converter. Using this technique the offset and 1/f flicker noise are modulated away from DC. For the ΣΔ switched-capacitor modulator, the correlated double sampling technique has been used for the amplifier of the integrator, which is the most critical element of the modulator. The ASIC, which has a current consumption of approximately 6 mA, is powered by the space-qualified version of LM117 component, which is a radiation tolerant three-terminal adjustable output linear regulator providing 5.7V output, the analog and digital cores operate at 3.3V internally while the I/O is performed at 5.7V level. The device provides two 32-bit digital outputs accessible by the serial interface: A non-calibrated capacitive measurement output and a temperature output as well as an analog output with 10-bit resolution. At system level, the requirement is to provide 0V at zero pressure and 5V output at maximum applied pressure (105% of max pressure range). At the first ASIC revision, a level translator from 3.3V to 5.7V was incorporated to up-convert the PWM output and the RC filtering was performed externally. The output stage of the level-converter was using an inverter with high-voltage transistors. Due to total dose irradiation the off-resistance of the high voltage NMOS transistor was decreasing giving rise to a higher current. The increased sink current was creating a smaller output swing at the PWM output, thus affecting the output voltage. At the second ASIC revision, the PWM output scheme is redesigned. The digital PWM output is filtered internally and the filtered output is applied to a closed-loop amplification stage. In this configuration the output voltage is merely set by the ratio of the input and feedback resistors. In order to address the problem of SEE the Triple Module Redundancy method with voting has been adopted. This technique has been applied at the level of digital synthesis. The TMR technique has been applied to all flip-flops of the digital part. In order to address the problem of SEL in the digital part, a library of custom digital cells has been designed and characterized in house to enhance radiation tolerance. It is a 3.3V junction isolated, low power library and contains combinational, sequential and special cells. In the analog part, all PMOS devices have been enclosed by N-type guard rings and all the NMOS devices have been enclosed by P-type guard rings. The size of the ASIC is 3mm x 2 mm and has been manufactured and tested. After electrical characterization the irradiation campaign took place. The TID experiment was performed using ten DUTs at the ESTEC Co-60 Facility up to 100 Krad. The DUTs electrical parameters were measured before irradiation, then they were subjected to 6 pre-specified irradiation dose steps and critical electrical parameters were measured after each step to investigate potential variations in performance. Afterwards, two annealing steps followed. The electrical parameters of the DUTs were measured after 24h and 168h of operation at room temperature. The experiment then concluded with an accelerated ageing test. Preliminary TID results have shown that the digital outputs are not affected by TID. As far as the analog output is concerned, a small error is related to the dependency of an internal bias voltage to the internal voltage generated by a bandgap reference circuit. This is because of the bipolar transistors, which suffer from radiation–induced leakage current. The holes trapped in the thick Shallow Trench Isolation (STI) oxide lead to an increase in the leakage current, which occurs at the interface between STI oxide and p-doped regions. The ASIC has also been tested for SEL/SET in the UCL cyclotron accelerator facility at worst case conditions (maximum voltage supply, 85 °C). The ASIC exhibited immunity when exposed to irradiation heavy ions C, Ne, Ar, Ni, Kr, Xe. Finally, the ASIC has been exposed to a Displacement Damage at UCL facility exhibiting robustness after exposure to 62 MeV proton fluence of 2E11 #/cm2 with a maximum flux of 2E8 #/cm2-s. Currently, the ASIC is being used to create engineering models of the space transmitter, which will be calibrated and then undergo mechanical and stress tests. In conclusion, robustness of the ASIC to Single Event Effects (SEL and SEU) has been proven through the irradiation campaign due to the appropriate design approach at different levels (physical, architectural). In order to minimize TID effects and further enhance radiation tolerance, an optimization of the bandgap reference generator using Enclosed Layout Transistor (ELT) could be supportive.

Peer reviewing

Paper

Accepted on 11 Jun 2018 by Boris Glass

Paper files:

• A_rad-hard_signal_conditioning_ASIC_for_space_grade_transducers-paper.docx