Speakers
Mr
Dimitris Mitrovgenis
(Senior IC Designer)Mr
Theodoros Athanassopoulos
(Technical Director)
Description
European Sensor Systems S.A is a global developer and manufacturer of high quality sensors based on MEMS. In the course of an ESA activity, titled “Space Qualified Family of MEMS Pressure Modules for Satellite Applications”, European Sensor Systems S.A is developing a custom radiation-hardened capacitive sensor signal conditioning ASIC for interfacing with the MEMS pressure sensors. The ASIC is built using X-FAB XH018 Process Design Kit, a 0.18 micron Modular Mixed Signal HV CMOS Technology. This paper presents a detailed procedure for radiation mitigation against Single Event Latch-up (SEL) effects at physical implementation level and the results of the irradiation campaign at UCL cyclotron.
A SEL is the result of the triggering of a parasitic thyristor (PNPN or NPNP structures) mainly existing in CMOS circuits. When it occurs, a high current flows from voltage supply to ground and if the power supply is maintained, the device can be destroyed by thermal effect. The mechanism is well documented in the literature [1].
In the analog part, preventing latch-up from occurring was done by reducing the gain of the two parasitic transistors by increasing the distance between the two parasitic complementary transistors where possible, reducing parasitic well and substrate resistors by using low resistance ground contacts and by surrounding MOS transistors with guard rings. In practice, all PMOS devices have been enclosed by N-type guard rings and all the NMOS devices have been enclosed by P-type guard rings.
For the digital part a SEL immune library was required. At that time, the IMEC DARE180X [2] was under development and not fully tested, so it was decided to build a custom on-site library immune to SEL allowing full control of synthesis and place and route procedures. The library ESS180RH consisting of digital cells has been designed and characterized in house to enhance radiation tolerance. It is a 3.3V junction isolated, low power library and contains combinational (logic gates), sequential (scan flip-flops) and special cells (layout fillers, antenna protection cells, level shifters). In the layout the triple well NMOS and PMOS devices have been surrounded by P-type and N-type guard rings respectively. The increase of the layout area compared to a conventional cell varies from 2x to 4x.
More specifically, after the layout of each cell is finished, a Library Exchange Format (LEF) file is generated, which includes design rules and abstract information about the cells.
An RC parasitic extraction is performed in order to obtain an extracted netlist for analog simulations. The purpose of this step is to perform the modelling of interconnects (resistive and capacitive parasitics) and capturing of the Layout Dependent Effects (LDE) that affect the transistor characteristics and depend on layout placement.
The extracted netlist of each cell is then used to perform analog simulations. The output of this step is the creation of the Liberty™ library format, which is an ASCII representation of the timing and power parameters associated with each cell. The timing and power parameters are obtained by simulating the cells under a variety of conditions (Process Voltage Temperature) corners and are used for static timing analysis and power analysis. It contains timing models and data to calculate I/O delay paths, timing check values, interconnect delays.
The structure of the .lib file is quite complex. The detailed description of the .lib file and the derivation of the timings is out of the scope of this document. Instead some important aspects are described here for the combinational and sequential cells. The timing characterization is performed using a two-dimensional timing model where the two independent axis variable are input slew and output load capacitance. This means that a two-dimensional matrix is created for each metric, where each row corresponds to the Input Slew and each column to the Output load capacitance.
The ASIC was manufactured and tested for SEL in the UCL cyclotron accelerator facility at worst case conditions (maximum voltage supply 3.6V, 85 °C). The ASIC exhibited immunity when the heavy ions shown in Table 1 were used as irradiation sources.
![enter image description here][1]
To conclude with, preventing SEL to occur demanded interventions at physical level. For the analog part the solution is quite common. As far as the digital part is concerned, a new 3.3V digital library ESS180RH has been created based on custom layout, parasitic extraction, simulation of the cells and generation of appropriate timing and layout files. The procedure for the creation of the library is fully automated and script-based once the layout is completed and can be easily applied to other foundries or PDK flavors.
1. European Cooperation for Space Standardization, Space product
assurance, Techniques for radiation effects mitigation in ASICs and
FPGAs handbook, ECSS-Q-HB-60-02A, September 2016
2. IMEC, DARE180X, http://dare.imec-int.com/en/technologies/dare180x [Accessed on
10/2/2018]
[1]: https://i.imgur.com/QTwQScr.png
Primary authors
Mr
Dimitris Mitrovgenis
(Senior IC Designer)
Mr
Theodoros Athanassopoulos
(Technical Director)
Co-authors
Mr
Antonis Depastas
(Mechanical Engineer)
Mr
Dimitris Zaxarias
(Lab Engineer)
Dr
Emmanuil Zervakis
(General Director)
Mrs
Katerina Spiropoulou
(Senior MEMS Designer)
Dr
Panagiotis Broutas
(MEMS Designer)
Mr
Panagiotis Vlagopoulos
(Design Engieer)
Mr
Stavros Filippas
(Lab Engineer)
Mr
Stylianos Polymenakos
(Production Supervisor)
