17–20 Jun 2018
Leuven, Belgium
Europe/Brussels timezone
On-site registration will be possible on Monday, June 18, 08:30 to 10:00

ATMX150RHA Circuit Design Platform

20 Jun 2018, 11:45
25m
IMEC (Leuven, Belgium)

IMEC

Leuven, Belgium

Kapeldreef 75 3001 Heverlee Belgium
Oral Implementation of Radiation Hardening on analogue circuits at cell-, circuit-, and system design level Radiation Hardened Technologies

Speaker

Mr Erwann BERLIVET (Atmel/Microchip)

Description

Microchip Technology Inc. is a leading provider of microcontroller and analog semiconductors, providing 150nm SOI technology (ATMX150RHA) for space product design. We manage full space product supply chain till qualified packaged products according to agencies standards, including foundry and ASIC design services. Building on ATC18RHA heritage, the ATMX150RHA design platform extend possibilities from digital to analog and mixed signal circuit design. To ease SoC design, Microchip provide qualified radiation hardened libraries of IOs, standard cells and analog IPs. Qualified domain extension to analog macros, use a strategy based on enhanced Standard Evaluation Circuit and dedicated test vehicle. Our enhanced Standard Evaluation Circuit contains digital requirements to qualify our technology up to 22M gates, analog monitoring cells, and a set of representative analog IPs. Our test vehicles are used to characterize analog IPs in a standalone mode, for electrical characteristics, radiation robustness and life time. A first set of IPs have been design and successfully qualified. These IPs are: - a linear voltage regulator, including power monitoring features - an analog multiplexer - an internal oscillator - a bandgap voltage reference We will present our results. In order to support analog or digital on top design flows, we provide packages containing libraries (IOs, standard cells and IPs). For digital design flow, physical, timing and behavioral models are provided. For analog design flow, we provide IOs and standard layouts and schematics. Regarding IPs, a black box layout and encrypted spice netlist are provided to allow integration and simulation

Primary author

Mr Erwann BERLIVET (Atmel/Microchip)

Presentation materials