Speaker
Mr
Dimitrios Baramilis
(ISD S.A.)
Description
The aim of this project is to provide Pulse Width Modulator controller solution that
will largely simplify Electronic Power Conditioners (EPC) design due to variety of
converter topologies that can be realized within one chip and decrease its cost due to
integration of more converter elements in one chip. Field of application of our PWM
controller can be far greater than EPCs only, ranging from platform to payload units.
It can be used in various topologies (Buck, Boost, Buck-Boost, Push-Pull, Flyback
and Forward converters) and their synchronous variations. Commonly used
regulation control loop is available (voltage mode and current mode). The Pulse
Width Modulator ASIC operates with clock signal (externally or internally generated)
ranging from 100 kHz to 1 MHz. The internally generated clock is available on an
external pin which enables to run other MISAC PWMs for multiphase converters.
The clock signal can be shifted by 90, 180 or 270 degrees and can be scaled down up
to 8 times. It has one independent voltage reference source (1.25V) and an output pin
with an 11mA maximum available current. For PWM signal generation it uses an
internal sawtooth generator with its slope trimmable by external components. The
Leading edge blanking internal circuit is applied to the current monitoring signal to
suppress voltage spikes. The leading edge blanking time, the maximum duty cycle
and the minimum duty cycle can be externally configured. Only passive components
are needed to for all configurations. PWM output features two 9V to 16V output
drivers designed to source and sink high peak currents (up to 2.5A) from capacitive
loads, such as the gate of a power MOSFET. The outputs can have four different
modes of operation as the needs of the application (single or dual output, alternate,
opposite and complimentary). The power supply of the output stage is independent
and isolated from the power supply of the rest of the ASIC circuit. Protection
circuitry includes a current limiter pulse-by-pulse operation with a 1.25V threshold, a
TTL compatible shutdown port, output overvoltage protection circuit and a soft start
pin. An under voltage lock-out circuit is used with 600mV hysteresis. The pulse
width modulator is implemented in a rad-tolerant 150nm CMOS-SOI process. The
ASIC has been radiation-hardened by design techniques (including Triple-Modular-
Redundancy, SET filtering, periodic reset with no operation interruption). The project
is currently at the start of first samples manufacturing phase.
Primary author
Mr
Dimitrios Baramilis
(ISD S.A.)
Co-authors
Dr
Constantin Papadas
(ISD SA)
Mr
David Levacq
(ESA – ESTEC)
Mr
Efthimios Karaolis
(ISD S.A.)
Mr
Michail Tourloukis
(ESA - ESTEC)
Ms
Pagona Bampali
(ISD S.A.)
Mr
Radoslav Darakchiev
(Astri Polska)
Peer reviewing
Paper
Paper files: