Speaker
Description
NASA’s Office of the Chief Technologist has recently developed a set of Strategic Technology Roadmaps that call out the need for more capable on-board flight computing. Future missions will necessitate robust and reliable on-board computing elements to execute the functions of pinpoint landing and hazard avoidance, and rendezvous-proximity operations-capture. The success if these types of missions is directly tied to the availability of high-performance space-qualified computing elements. Similar to ESA, NASA understands that advances in high performance, low-power onboard computers are central to more capable space operations in support of robotic science, robotic spacecraft servicing, and crewed exploration missions. Many of the complex objectives of future missions can be mitigated by making decisions in the in-situ flight environment on-board the spacecraft. This goal is coupled with the widespread need for increased autonomy on all classes of missions, especially for the functions of autonomous Guidance, Navigation, and Control.
In particular advanced space-qualified on-board processor performance requirements will be driven by the challenges of the optical (vision-based) terrain-relative navigation functions that are intrinsic to performing autonomous planetary and small body landing and hazard avoidance functions as well as the similar optical target-relative navigation functions that permit autonomous space rendezvous, proximity operations and docking. Advanced on-board computing is of high importance to NASA since optical Terrain Relative Navigation (TRN) systems are baselined on upcoming robotic landing missions to the Moon and Mars. Likewise there is an Intelligent Lander System (ILS) in development at NASA JPL for a Europa lander concept. JPL is also developing a Lander Vision System (LVS) for the Mars 2020 mission. In addition the need to perform autonomous in-orbit space platform assembly and servicing as well as in-flight planetary/small body sample retrieval also imposes a significant demand for on-board optical navigation processing capability. Beyond just achieving higher processing capabilities the Size, Weight and Power (SWaP) requirements for on-board computing elements will also need to be directly addressed, especially for the significantly mass constrained planetary/small body exploration and landing missions.
This proposed OBDP2019 presentation will cover three distinct, but closely related, areas. In the first part of this presentation a brief summary of the NASA technology roadmaps for advanced space computing will be provided and the current set of driving requirements will be defined.
In the second part of this presentation the on-going work that NASA’s Space Technology Mission Directorate (STMD) is sponsoring to develop a High Performance Spaceflight Computing (HPSC) “chiplet” will be discussed. The HPSC chiplet is a 64-bit RISC multicore radiation-hard flight processing chip for use within a general purpose processor. Briefly stated the HPSC chiplet technology is conceived, in a reference spacecraft avionics architecture, as a dual quad-core building block, with provisions for extensibility and interoperability with other computing devices, and with native architectural support for power scaling and energy management, as well as hosting of software-based fault tolerance methods. A multi-year technology development plan has been formulated by NASA and our industrial partner (the Boeing Company) which is expected to deliver a next-generation rad-hard space processor based on the ARM processor architecture that will provide optimal power-to-performance for upgradeability, software availability, ease of use, and affordability. The HPSC project will use Radiation Hard By Design (RHBD) standard cell libraries, as well as the ARM A53 processor with its internal NEON Single Instruction Multiple Data (SIMD) design. The ultimate goal of NASA’s HPSC activities is to develop a next-generation flight computing system addressing the computational performance, energy management, and fault tolerance needs of NASA missions through 2030. A description will be provided of an envisioned Descent & Landing Computer (DLC) which will be architected to include the HPSC multicore ARM A53 plus Field-Programmable Gate Arrays (FPGAs) as well as multiple interfaces for navigation sensors such as lidars, laser altimeters, visible and infrared cameras, and IMUs. This DLC technology is currently at TRL 3 with plans to be matured to TRL 5 by FY2020.
The third portion of this presentation will consist of into the future, well beyond the current HPSC technology. A new and higher requirements bar will be described to meet the on-board processing challenges to support optical navigation and other GN&C critical functions (e.g. autonomous low-thrust guidance, autonomous maneuver planning, autonomous fault protection) in the time frame beyond 2030. The need for reconfigurable computing capabilities for supporting various GN&C functions will also be discussed in this third and last section of the presentation.
| Paper submission | Yes |
|---|
