25–27 Feb 2019
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone

Reliable multi-processor hardware design

27 Feb 2019, 11:30
20m
Erasmus (European Space Research and Technology Centre (ESTEC))

Erasmus

European Space Research and Technology Centre (ESTEC)

ESTEC (European Space Research & Technology Centre) Keplerlaan 1 2201 AZ Noordwijk The Netherlands Tel: +31 (0)71 565 6565
Oral presentation Devices and IP for On-Board Data Processing Devices and IP for On-Board Data Processing

Speaker

Dr Gerard Rauwerda (Technolution B.V.)

Description

Technolution is a technology integrator who deploys multidisciplinary expertise in an effective way to find the best technology solution for its customers. We develop among others high-speed digital signal processing electronics, programmable logic, embedded hardware and software solutions for imaging, video, semiconductor and security applications. In some solutions we (re)use our softcore IPs for FPGA and ASIC: the FreNox RISC-V processor and the Xentium Digital Signal Processor (DSP).

The multitude of high-speed processing applications all require multi-core processor architectures with varying requirements on real-time performance, flexibility, safety and security. We will present multiple hardware design cases; real-time imaging for e-beam lithography used in semiconductor lithography machines, which is massively parallel, highly configurable and generates a net output data stream of 3 Tbit/s; and our security platform JelloPrime, which uses a softcore version of the FreNox RISC-V processor for all configuration and control and dedicated hardware acceleration for the data encryption/decryption.

Our Xentium DSP and fault-tolerant Network-on-Chip (NoC) IP have been designed targeting the next-generation DSP roadmap for Space. Next generation payload processing ASICs for space applications have to be programmable, high performance and low power. Moreover, the digital signal processors have to be tightly integrated with space relevant interfaces in heterogeneous System-on-Chip (SoC) solutions with the required fault tolerance and radiation hardness.

While combining our multidisciplinary high-speed and secure digital processing expertise (for non-space high-demanding applications) and reusing our softcore IP building blocks (Xentium DSP, FreNoX RISC-V, NoC), we present how to create multi-processor architectures for on-board payload data processing applications. We also address the programming aspects of such distributed multi-processor architectures.

Paper submission Yes

Primary authors

Dr Gerard Rauwerda (Technolution B.V.) Dr Edwin Hakkennes (Technolution B.V.) Jonathan Hofman (Technolution B.V.) Serge de Vos (Technolution B.V.)

Presentation materials