Speaker
Description
The development of High Performance Processing capability is necessary to face future space application needs. One of the technology path explored by Airbus Defence and Space is to build generic and flexible platforms enabling the use of Commercial Off The Shelf (COTS) components through appropriate and scalable radiations effects mitigation techniques. The ESA study “High performance COTS Based Computer” has validated an architectural concept with a prototype implementation. This concept with a mitigation mechanism based on a SmartIO element implementing the monitoring and error mitigation functions has been applied and tailored for being implemented on key programmes: COTS ARM processors and reconfigurable FPGA devices are now used within e.g. central computers products for LEO orbit or within high performance instrument processing devices in GEO.
The COTS Based Reliable Architecture (COBRA) is one of the in-going development of the Airbus Defence and Space Real-Time Lab in Toulouse. This development targets a new generation of very high performance generic and scalable fault-tolerant architecture demonstrator for on-board payload processing with cost and power consumption containment by enabling the use on-board of the last generation of MPSoC devices that features extremely high performances. A TRL 4 demonstrator has been developed with Xilinx Zynq UltraScale+ devices and Serial Rapid IO data links to achieve multi-Gbps of processed data throughput and is currently being evaluated. The first evaluation results will be presented with the application use case developed for Vision Based Navigation in support to robotic applications. Further use cases may also apply in the future for various on-board processing domains such as image, telecom or radar signals or for supporting innovative algorithms aiming at e.g. artificial intelligence on-board.
Summary
Presentation of the COTS Based Reliable Architecture (COBRA) demonstrator targeting a next generation of very high performance generic and scalable fault-tolerant architecture demonstrator for on-board payload processing using Xilinx Zynq Ultrascale+ and Serial RapidIO data links.
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