Speaker
Description
Reconfigurable architectures can enhance on-board processing with unprecedented levels of flexibility, enabling the adaptation of the system to functional and/or fault-tolerance requirements that may change during mission lifetime. When combined with commercial off-the-shelf (COTS) devices, they lead to cost-effective solutions which can benefit from state-of-the-art devices and technologies. However, additional fault-tolerance mechanisms are required to maintain the reliability rad-hard devices provide.
In this work, a Reconfigurable Video Processor (RVP) for space applications has been implemented on a Zynq UltraScale+ device. The diversity of computing fabrics is exploited to harden the system against the occurrence of SEUs and to improve the performance of certain tasks using hardware acceleration. In fact, the ARTICo3 architecture is available in the hardware fabric, enabling run-time tradeoffs between computing performance, energy efficiency and fault tolerance. Hierarchical scrubbers (slow software-based readback scrubbers, fast hardware-based error redundancy coding scrubber) complement the hardware redundancy provided by ARTICo3. The software fabric relies on the RTEMS operating system running on the Cortex-R5 processors operating in lock-step mode to ensure real-time behaviour.
As an example, a lossy hyperspectral image compressor based on the CCSDS123.1 standard has been implemented. This application is executed using a variable number of hardware accelerators, obtaining a speedup of 10x when compared against a software-based implementation. Moreover, all fault mitigation techniques have been tested using fault injection to change the configuration memory of the FPGA. The design of the platform, algorithms and hardware/software components has been driven by industrial requirements in the context of the ENABLE-S3 project (ECSEL).
| Paper submission | Yes |
|---|
