25–27 Feb 2019
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone

ON-BOARD COMPLEX IMAGE PROCESSING BASED ON FPGA ACCELERATION FOR AUTONMOUS NAVIGATION IN SPACE

27 Feb 2019, 14:20
20m
Erasmus (European Space Research and Technology Centre (ESTEC))

Erasmus

European Space Research and Technology Centre (ESTEC)

ESTEC (European Space Research & Technology Centre) Keplerlaan 1 2201 AZ Noordwijk The Netherlands Tel: +31 (0)71 565 6565
Oral presentation On-Board Processing Algorithms On-Board Processing Algorithms

Speaker

Mr Paul Bajanaru (GMV Innovating Solutions)

Description

GMV works in many activities aimed at developing, validating and verifying up to TRL-5 advanced GNC and image processing algorithms to process autonomously on-board of a spacecraft a Vision-Based Navigation system for Descent & Landing scenario to small bodies. For the last year GMV has been developing under ESA activity the Engineering Model (EM) of the Vision-Based Navigation Camera (VNBC) for Phobos Sample Return (PhSR) mission which is validated and verified form, fit and function in representative environment to reach TRL-6. The VBNC solution is based on detection and tracking of remarkable features in images of Phobos surface. Wide trade-offs were performed over the optimal algorithms and on-board HW processing architecture based on high-fidelity closed-loop simulation and breadboarding on representative flight avionics. The project involves HW development of VBNC elements in high-performance avionics architecture including HW/SW implementation of VBN algorithms. The Navigation Sensor includes Engineering Model (EM) of the Image Processing Board (IPB) and Elegant BreadBoard (EBB) of Camera Optical Unit (COU).
The IPB-EM is the main contribution of this activity. IPB includes two FPGAs, a small and reliable rad-hard European FPGA dedicated to interfaces control unit and monitoring of the IPB, the other is a large rad-hard FPGA including complex processing of images to extract navigation data. The Interfaces FPGA selected is fully rad-hard European BRAVE FPGA. The large Processing FPGA copes with very demanding on-board image processing and hence a high-performance, high-density rad-hard V5QV FPGA is selected. Image processing is implemented on FPGA with performance improvement of ~200x speed-up compared to space processors. The IPB-EM is fully validated including modes, interfaces, management and image processing. The validation campaign includes IPB-EM thermal pre-tests, radiation and mechanical analysis. Functional tests will be performed from Model-in-the-loop to HW-in-the-loop, using a Graphical User Interface simulator, Phobos 3D-model and Phobian-like surface mock-up with HW-in-the-loop dynamic set-up in GMV’s plaftorm-ART® facilities by using robotic arm and cartesian robotic illumination rails. The VBNC HW is mounted on top of the robotic arm emulating Phobos environment and spacecraft dynamics. The COU provides representative optics needed for the validation and interfacing of IPB. Selected detector is CMV4000 (4K-pixels) as per PhSR mission. Optics FOV is selected as trade-off solution between QSO-operations and Navigation processing requirements. Best compromise is 20º FOV. COU-EBB implements low-level image correction functionalities including binning capability which is used to obtaine 2 different FOV with same optics and detector. For QSO operations cropping center 1024x1024 pixels provides a 10º FOV while for Descent and Landing binning the full-size 2048x2048 to 1024x1024 pixels provides the initial 20º FOV.

Summary

On-board high-performance computation based on HW acceleration by means of radiation hardened FPGA is presented in order to show the capabilities for critical GNC operations on autonomous vision-based navigation system for Descent & Landing scenario to small bodies. For the last year GMV has been developing under ESA activity the Engineering Model (EM) of the Vision-Based Navigation Camera (VNBC) for Phobos Sample Return (PhSR) mission which is validated and verified form, fit and function in representative environment to reach TRL-6. The main product of this project is the Image Processing Board based on two FPGA, new European NG-MEDIUM BRAVE FPGA and consolidated Xilinx Virtex-5QV.

Paper submission Yes

Primary authors

David Gonzalez-Arjona (GMV Aerospace and Defence) Mr Ruben Domingo (GMV Aerospace and Defence) Mr Paul Bajanaru (GMV Innovating Solutions)

Co-authors

Mr Florin-Adrian Stancu (GMV Innovating Solutions SLR) Mr Andrei Alexe (GMV Innovating Solutions SLR) Mr Sergiu Sincan (GMV Innovating Solutions SLR) Mr Dragos Gogu (GMV Innovating Solutions SLR)

Presentation materials